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DLPC900_V01 Datasheet(Hoja de datos) 59 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 59 page
background image
Host
DLPC900
USB
JTAG
LEDs
Digital Receiver
HDMI
DISPLAYPORT
Camera
Crystal
I2C
Parallel
Flash
LED
Status
Power
Management
P1_B[9:0]
P1_A[9:0]
P1A_CLK, P1_DATEN,
P1_VSYNC, P1_HSYNC
P1_C[9:0]
I2C
HDMI
DMD_A,B[15:0]
DMD Control
DMD SSP
LED EN[2:0]
LED PWM[2:0]
FAN
PWM
VCC
PWRGOOD
POSENSE
TRIG_IN[1:0]
TRIG_OUT[1:0]
I2C_SCL0, I2C_SDA0
USB_DN,DP
PM_ADDR[22:0],WE
DATA[15:0],OE,CS
HEARTBEAT
FAULT_STATUS
MOSC
POWER RAILS
12V DC IN
I2C_SCL1
I2C_SDA1
TDO[1:0],TRST,TCK
RMS[1:0],RTCK
DP
RAM
GUI
DLP6500FYE
59
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
8.2.2 Typical Single Controller Chipset
A typical embedded system application using the DLPC900 controller and DLP6500 is shown in Figure 34. This
configuration uses one DLPC900 controller to operate with a DLP6500 and supports a 24-bit parallel RGB input,
typical of LCD interfaces, from an external source or processor.
This system supports both still and motion video sources. However, the controller only supports sources with
periodic synchronization pulses. This is ideal for motion video sources, but can also be used for still images by
maintaining periodic syncs and only sending a new frame of data when needed. The still image must be fully
contained within a single video frame and meet the frame timing constraints. The DLPC900 controller refreshes
the displayed image at the source frame rate and repeats the last active frame for intervals in which no new
frame has been received.
This configuration also supports the high speed sequential pattern modes mentioned in the Structured Light
Application. The patterns can be from the video source, from the USB or I2C interface, or pre-stored in external
flash, and have a maximum of 24 bits per pixel. The patterns are pre-loaded into the internal embedded DRAM
and then streamed to the DLP6500 at high speeds.
Figure 34. Typical Application Schematic for DLP6500




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