Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼
Nombre de pieza
         Descripción


DLPC900_V01 Datasheet(Hoja de datos) 6 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo 

 6 page
background image
6
DLPC900
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
www.ti.com
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
(1)
Refer to I/O Type and Subscript Definition (Table 1).
Initialization Pin Functions
PIN
I/O
POWER
I/O
TYPE(1)
CLK
SYSTEM
DESCRIPTION
NAME
NUMBER
POSENSE
P22
VDD33
I4
H
Async
Power-On Sense is an active high signal with hysteresis, that
is generated from an external voltage monitor circuit. This
signal should be driven active high when all the controller
supply voltages have reached 90% of their specified
minimum voltage. This signal should be driven inactive low
after the falling edge of PWRGOOD as shown in . Refer to
Power-Up and Power-Down Timing Requirements for more
details.
PWRGOOD
T26
VDD33
I4
H
Async
Power Good is an active high signal with hysteresis that is
provided from an external voltage monitor circuit. A high
value indicates all power is within operating voltage
specifications and the system is safe to exit its RESET state.
Refer to Power-Up and Power-Down Timing Requirements
for more details.
EXT_ARSTZ
T24
VDD33
O2
Async
General purpose active low reset output signal. This output is
driven low immediately after POSENSE is externally driven
low, placing the system in RESET and remains low while
POSENSE remains low. EXT_ARSTZ will continue to be
held low after POSENSE is driven high and released by the
controller firmware. EXT_ARSTZ is also driven low
approximately 5 µs after the detection of a PWRGOOD or
any internally generated reset. In all cases, it will remain
active for a minimum of 2 ms.
CTRL_ARSTZ
T25
VDD33
O2
Async
Controller active low reset output signal. This output is driven
low immediately after POSENSE is externally driven low and
remains low while POSENSE remains low. CTRL_ARSTZ
will continue to be held low after POSENSE is driven high
and released by the controller firmware. CTRL_ARSTZ is
also optionally asserted low approximately 5 µs after the
detection of a PWRGOOD or any internally generated reset.
In all cases it will remain active for a minimum of 2 ms.




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83 


Datasheet Download




Enlace URL

¿ALLDATASHEET es útil para Ud.?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl