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DLPC900_V01 Datasheet(Hoja de datos) 63 Page - Texas Instruments
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TI1 [Texas Instruments]
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DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
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Copyright © 2014–2019, Texas Instruments Incorporated
System Power-Up Sequence (continued)
It is strongly recommended that a 0.5-W external series resistance (of 22 Ω) to limit the potential impact of a
continuous short circuit between either USB D+ or USB D– to either Vbus, GND, the other data line, or the cable.
For additional protection, also add an optional 200-mA Schottky diode from USB_DAT to VDD33.
9.4 System Reset Operation
9.4.1 Power-Up Reset Operation
Immediately after a power-up event, DLPC900 hardware will automatically bring up the master PLL and place the
controller in normal power mode. It will then follow the standard system reset procedure (see System Reset
9.4.2 System Reset Operation
Immediately after any type of system reset (power-up reset, PWRGOOD reset, watchdog timer time-out, and so
forth), the DLPC900 automatically returns to normal power mode and returns to the following state:
All GPIO will tri-state.
The master PLL will remain active (it is only reset on a power-up reset) and most of the derived clocks will be
active. However, only those resets associated with the DLPC900 processor and its peripherals will be
released. (The DPLC900 firmware is responsible for releasing all other resets).
The DLPC900 associated clocks will default to their full clock rates (boot-up is at full speed).
The PLL feeding the LVDS DMD interface (PLLD) will default to its power-down mode and all derived clocks
will be inactive with corresponding resets asserted. (The DLPC900 firmware is responsible for enabling these
clocks and releasing associated resets).
LVDS I/O will default to its power-down mode with tri-stated outputs.
All resets output by the DLPC900 will remain asserted until released by the firmware (after boot-up).
The DLPC900 processor will boot-up from external flash.
Once the DLPC900 processor boots-up, the DLPC900 firmware will:
Configure the programmable DDR clock generator (DCG) clock rates (that is, the DMD LVDS interface rate)
Enable the DCG PLL (PLLD) while holding divider logic in reset
After the DCG PLL locks, the processor software will set DMD clock rates
API software will then release DCG divider logic resets, which in turn, will enable all derived DCG clocks
Release external resets
The LVDS I/O is reset by a system reset event and remains in reset until released by the DLPC900 firmware.
Thus, the software is responsible for waiting until power is restored to these components before releasing reset.
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