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DLPC900_V01 Datasheet(Hoja de datos) 71 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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71
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Table 17. DMD Interface Specific PCB Routing
SIGNAL GROUP LENGTH MATCHING
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH
UNIT
DMD
(LVDS)
SCA_P/ SCA_N
DDA_P_(15:0)/ DDA_N_(15:0)
DCKA_P/ DCKA_N
± 150
(± 3.81)
mil
(mm)
DMD
(LVDS)
SCB_P/ SCB_N
DDB_P_(15:0)/ DDB_N_(15:0)
DCKB_P/ DCKB_N
± 150
(± 3.81)
mil
(mm)
When routing the DMD Interface signals it is recommended to:
Minimize the number of layer changes for Single-ended signals.
Individual differential pairs can be routed on different layers but the signals of a given pair should not change
layers.
(1)
Max signal routing length includes escape routing.
Table 18. DMD Signal Routing Length(1)
BUS
MIN
MAX
UNIT
DMD
(LVDS)
50
375
mm
Stubs: Stubs should be avoided.
Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω
internally.
Connector (DMD-LVDS interface bus only):
High-speed connectors that meet the following requirements should be used:
Differential crosstalk: < 5%
Differential impedance: 75 to 125 Ω
Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed
in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference
for each row should be accounted for on associated PCB etch lengths.
These guidelines will produce a maximum PCB routing mismatch of 4.41 mm (0.174 inch) or approximately 30.4
ps, assuming 175 ps/inch FR4 propagation delay.
These PCB routing guidelines will result in approximately 25-ps system setup margin and 25-ps system hold
margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.
Both the DLPC900 output timing parameters and the DMD input timing parameters include timing budget to
account for their respective internal package routing skew.
10.1.8.1 Flex Connector Plating
Plate all the pad area on top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of
electrolytic hard gold over a minimum of 100 micro-inches of electrolytic nickel.




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