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DLPC900_V01 Datasheet(Hoja de datos) 73 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 73 page
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73
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
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Copyright © 2014–2019, Texas Instruments Incorporated
10.1.12 Trace Impedance and Routing Priority
For best performance, it is recommended that the trace impedance for differential signals as in Table 21.
All signals should be 50-Ω controlled impedance unless otherwise noted in Table 21.
Table 21. Trace Impedance
SIGNAL ON PIN
DIFFERENTIAL IMPEDANCE
DCKA_(P,N)
100 Ω ±10%
SCA_(P,N)
DDA_(P,N)_(15:00)
DCKB_(P,N)
100 Ω ±10%
SCB_(P,N)
DDB_(P,N)_(15:00)
USB_DAT_(P,N)
90 Ω ±10%
USB_(P,N)
All other Differential Signals
100 Ω ±10%
(1)
Refer to Table 8 for length matching requirement
(2)
Switching layer should not be done except at the beginning and end of the trace
(3)
Maximum routing length of 2 inches for each signal/pair, includes escape routing
(4)
Keep routing length under 0.35 inches
Table 22 lists the signals’ routing priority assignment.
Table 22. Routing Priority
SIGNAL ON PIN
PRIORITY
DCKA_(P,N) SCA_(P,N) DDA_(P,N)_(15:00) DCKB_(P,N)
SCB_(P,N) DDB_(P,N)_(15:00)
1 (1) (2) (3)
USB_(P,N) USB_DAT_(P,N)
2 (1)
P1(A,B,C)(9:2),P2(A,B,C)(9:2), P_CLK1, P_CLK2, P_CLK3,
P_DATEN1, P_DATEN2, P1_VSYNC, P2_VSYNC, P1_HSYNC,
P2_HSYNC
3 (1) (2) (3)
OCLKA, MOSCP
4 (4)
10.1.13 Power and Ground Planes
For best performance, the following are recommendations:
Solid ground planes between each signal routing layer
Two solid power planes for voltages
Power and ground pins should be connected to these planes through a via for each pin
All device pin and via connections to these planes should use a thermal relief with a minimum of four spokes
Trace lengths for the component power and ground pins should be minimized to 0.03 inches or less
Vias should be spaced out to avoid forming slots on the power planes
High speed signals should not cross over a slot in the adjacent power planes
Vias connecting all the digital layers should be placed around the edge of the rigid PCB regions 0.03 inches
from the board edges with 0.1 inch spacing prior to routing
Placing extra vias is not required if there are sufficient ground vias due to normal ground connections of
devices
All signal routing and signal vias should be inside the perimeter ring of ground vias
10.1.14 Power Vias
Power and Ground pins of each component shall be connected to the power and ground planes with a via for
each pin. Avoid sharing vias to the power plane among multiple power pins, where possible. Trace lengths for
component power and ground pins should be minimized (ideally, less than 0.100”). Unused or spare device pins
that are connected to power or ground may be connected together with a single via to power or ground. The
minimum spacing between vias shall be 0.050” to prevent slots from being developed on the ground plane.




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