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DLPC900_V01 Datasheet(Hoja de datos) 10 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 10 page
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10
DLPC900
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
www.ti.com
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
(1)
The default wait-state is set for a flash device of 120 ns access time. Therefore, the slowest flash access time supported is 120 ns.
Refer to the Program Memory Flash Interface on how to program new wait-state values.
(2)
Refer to I/O Type and Subscript Definition (Table 1).
(3)
Refer to the Figure 32 for the memory layout of the boot flash.
(4)
Requires an external 10-kΩ pullup resistor.
(5)
Requires an external 10-kΩ pulldown resistor.
Program Memory Flash Interface Pin Functions
PIN(1)
I/O
POWER
I/O TYPE
(2)
CLK SYSTEM
DESCRIPTION
NAME
NUMBER
CHIP SELECT 0
(ADDITIONAL
FLASH)
CHIP SELECT
1
(BOOT FLASH
ONLY) (3)
CHIP SELECT 2
(ADDITIONAL
FLASH)
PM_CSZ_0 (4)
D13
VDD33
O5
Async
Chip select
(active low)
N/A
N/A
PM_CSZ_1 (4)
E12
VDD33
O5
Async
N/A
Boot flash chip
select
(active low)
N/A
PM_CSZ_2 (4)
A13
VDD33
O5
Async
N/A
N/A
Chip select
(active low)
PM_ADDR_22 (5)
A12
VDD33
B5
Async
Address bit (MSB)
Address bit
(MSB)
Address bit (MSB)
PM_ADDR_21 (5)
E11
VDD33
B5
Async
Address bit
Address bit
Address bit
PM_ADDR_20
D12
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_19
C12
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_18
B11
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_17
A11
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_16
D11
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_15
C11
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_14
E10
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_13
D10
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_12
C10
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_11
B9
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_10
A9
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_9
E9
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_8
D9
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_7
C9
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_6
B8
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_5
A8
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_4
D8
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_3
C8
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_2
B7
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_1
A7
VDD33
O5
Async
Address bit
Address bit
Address bit
PM_ADDR_0
C7
VDD33
O5
Async
Address bit (LSB)
Address bit
(LSB)
Address bit (LSB)
PM_WEZ
B12
VDD33
O5
Async
Write-enable
(active low)
Write-enable
(active low)
Write-enable
(active low)
PM_OEZ
C13
VDD33
O5
Async
Output-enable
(active low)
Output-enable
(active low)
Output-enable
(active low)
PM_BLSZ_1
B6
VDD33
O5
Async
UpperByte(15:8)
enable
(active low)
N/A
UpperByte(15:8)
Enable
(active low)
PM_BLSZ_0
A6
VDD33
O5
Async
LowerByte(7:0)
enable
(active low)
N/A
LowerByte(7:0)
Enable
(active low)
PM_DATA_15
C17
VDD33
B5
Async
Data bit (15)
Data bit (15)
Data bit (15)
PM_DATA_14
B16
VDD33
B5
Async
Data bit (14)
Data bit (14)
Data bit (14)




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