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DLPC900 Datasheet(PDF) 12 Page - Texas Instruments |
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DLPC900 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 83 page  12 DLPC900 DLPS037D – OCTOBER 2014 – REVISED MARCH 2019 www.ti.com Product Folder Links: DLPC900 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated (1) Port 1 and Port 2 are capable of 24-bits each. A maximum of 8-bits is available in each of the A, B, and C channels. The 8-bit color input should be connected to bits [9:2] of the corresponding A, B, C input channels. Sources feeding 8-bits or less per color component channel should be MSB justified when connected to the DLPC900, and the LSBs tied to ground along with the data lines 0 and 1 from every channel. Three port clocks options (1, 2, and 3) are provided to improve the signal integrity. (2) Ports 1 and 2 can be used separately as two 24-bit ports, or can be combined into one 48-bit port (typically, for high data rate sources) for transmission of two pixels per clock. (3) The A, B, C input data channels of ports 1 and 2 can be internally reconfigured or remapped for optimum board layout. Specifically each channel can individually remapped to the internal GBR/ YCbCr channels. For example, G data can be connected to channel A, B, or C and remapped to be appropriate channel internally. Port configuration and channel multiplexing is handled in the API software. (4) Refer to I/O Type and Subscript Definition (Table 1). (5) Port 1 and Port 2 are capable of 24-bits each. A maximum of 8-bits is available in each of the A, B, and C channels. The 8-bit color input should be connected to bits [9:2] of the corresponding A, B, C input channels. Sources feeding 8-bits or less per color component channel should be MSB justified when connected to the DLPC900, and the LSBs tied to ground along with the data lines 0 and 1 from every channel. Three port clocks options (1, 2, and 3) are provided to improve the signal integrity. Port 1 and Port 2 Channel Data and Control Pin Functions PIN (1) (2) (3) I/O POWER I/O TYPE (4) CLK SYSTEM DESCRIPTION NAME NUMBER P_CLK1 AE22 VDD33 I4 D N/A Input port data pixel write clock (selectable as rising or falling edge triggered, and with which port it is associated (Port 1 or Port 2 or (Port 1 and Port 2))). P_CLK2 W25 VDD33 I4 D N/A Input port data pixel write clock (selectable as rising or falling edge triggered, and with which port it is associated (Port 1 or Port 2 or (Port 1 and Port 2))). P_CLK3 AF23 VDD33 I4 D N/A Input port data pixel write clock (selectable as rising or falling edge triggered, and with which port it is associated (Port 1 or Port 2 or (Port 1 and Port 2))). P_DATEN1 AF22 VDD33 I4 D P_CLK1, P_CLK2, or P_CLK3 Active high data enable. Selectable as to which port it is associated with (Port 1 or Port 2 or (Port 1 and Port 2)). P_DATEN2 W24 VDD33 I4 D P_CLK1, P_CLK2, or P_CLK3 Active high data enable. Selectable as to which port it is associated with (Port 1 or Port 2 or (Port 1 and Port 2)). P1_A9 P1_A8 P1_A7 P1_A6 P1_A5 P1_A4 P1_A3 P1_A2 P1_A1 (5) P1_A0 (5) AD15 AE15 AE14 AE13 AD13 AC13 AF14 AF13 AF12 AE12 VDD33 I4 D P_CLK1, P_CLK2, or P_CLK3 Port 1 A channel input pixel data (bit weight 128) Port 1 A channel input pixel data (bit weight 64) Port 1 A channel input pixel data (bit weight 32) Port 1 A channel input pixel data (bit weight 16) Port 1 A channel input pixel data (bit weight 8) Port 1 A channel input pixel data (bit weight 4) Port 1 A channel input pixel data (bit weight 2) Port 1 A channel input pixel data (bit weight 1) Unused, tie to 0 Unused, tie to 0 P1_B9 P1_B8 P1_B7 P1_B6 P1_B5 P1_B4 P1_B3 P1_B2 P1_B1 (5) P1_B0 (5) AF18 AB18 AC15 AC16 AD16 AE16 AF16 AF15 AC14 AD14 VDD33 I4 D P_CLK1, P_CLK2, or P_CLK3 Port 1 B channel input pixel data (bit weight 128) Port 1 B channel input pixel data (bit weight 64) Port 1 B channel input pixel data (bit weight 32) Port 1 B channel input pixel data (bit weight 16) Port 1 B channel input pixel data (bit weight 8) Port 1 B channel input pixel data (bit weight 4) Port 1 B channel input pixel data (bit weight 2) Port 1 B channel input pixel data (bit weight 1) Unused, tie to 0 Unused, tie to 0 P1_C9 P1_C8 P1_C7 P1_C6 P1_C5 P1_C4 P1_C3 P1_C2 P1_C1 (5) P1_C0 (5) AD20 AE20 AE21 AF21 AD19 AE19 AF19 AF20 AC19 AE18 VDD33 I4 D P_CLK1, P_CLK2, or P_CLK3 Port 1 C channel input pixel data (bit weight 128) Port 1 C channel input pixel data (bit weight 64) Port 1 C channel input pixel data (bit weight 32) Port 1 C channel input pixel data (bit weight 16) Port 1 C channel input pixel data (bit weight 8) Port 1 C channel input pixel data (bit weight 4) Port 1 C channel input pixel data (bit weight 2) Port 1 C channel input pixel data (bit weight 1) Unused, tie to 0 Unused, tie to 0 P1_VSYNC AC20 VDD33 B2 D P_CLK1, P_CLK2, or P_CLK3 Port 1 vertical sync. While intended to be associated with port 1, it can be programmed for use with port 2. |
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