Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼
Nombre de pieza
         Descripción


DLPC900AZPC Datasheet(Hoja de datos) 15 Page - Texas Instruments

Click here to check the latest version.
No. de Pieza. DLPC900AZPC
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo 

 15 page
background image
15
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
(1)
Refer to I/O Type and Subscript Definition (Table 1).
(2)
This signal does not apply to the slave controller in a two controller system configuration. On the slave controller, this pin is reserved
and should be left unconnected. Refer to Typical Single Controller Chipset and Typical Two Controller Chipset for a description between
a one controller and a two controller configuration.
Peripheral Interface Pin Functions
PIN
I/O
POWER
I/O TYPE
(1)
CLK SYSTEM
DESCRIPTION
NAME
NUMBER
I2C0_SCL
A10
VDD33
B8
N/A
I2C bus 0, clock. This bus supports 400 kHz, fast mode
operation. This input is not 5 V tolerant. This pin requires
an external pullup resistor to 3.3 V. The minimum
acceptable pullup value is 1 kΩ resistor.
I2C0_SDA
B10
VDD33
B8
I2C0_SCL
I2C bus 0, data. This bus supports 400 kHz, fast mode
operation. This input is not 5 V tolerant. This pin requires
an external pullup resistor to 3.3 V. The minimum
acceptable pullup value is 1 kΩ resistor.
I2C1_SDA (2)
E19
VDD33
B2
I2C1_SCL
I2C bus 1, data. This bus supports 400 kHz, fast mode
operation. This input is not 5 V tolerant. This pin requires
an external pullup resistor to 3.3 V. The minimum
acceptable pullup value is 1 kΩ resistor.
I2C1_SCL (2)
D20
VDD33
B2
N/A
I2C bus 1, clock. This bus supports 400 kHz, fast mode
operation. This input is not 5 V tolerant. This pin requires
an external pullup resistor to 3.3 V. The minimum
acceptable pullup value is 1 kΩ resistor.
I2C2_SDA (2)
C21
VDD33
B2
I2C2_SCL
I2C bus 2, data. This bus supports 400 kHz, fast mode
operation. This input is not 5 V tolerant. This pin requires
an external pullup resistor to 3.3 V. The minimum
acceptable pullup value is 1 kΩ resistor.
I2C2_SCL (2)
B22
VDD33
B2
N/A
I2C bus 2, clock. This bus supports 400 kHz, fast mode
operation. This input is not 5 V tolerant. This pin requires
an external pullup resistor to 3.3 V. The minimum
acceptable pullup value is 1 kΩ resistor.
SSP0_CLK
AD4
VDD33
B5
N/A
Synchronous serial port 0, clock
SSP0_RXD
AD5
VDD33
I4
SSP0_CLK
Synchronous serial port 0, receive data in
SSP0_TXD
AB7
VDD33
O5
SSP0_CLK
Synchronous serial port 0, transmit data out
SSP0_CSZ_0 (2)
AC5
VDD33
B5
SSP0_CLK
Synchronous serial port 0, chip select 0 (active low)
SSP0_CSZ_1 (2)
AB6
VDD33
B5
SSP0_CLK
Synchronous serial port 0, chip select 1 (active low)
This signal connects to the DMD SCP_ENZ input
SSP0_CSZ_2 (2)
AC3
VDD33
B5
SSP0_CLK
Synchronous serial port 0, chip select 2 (active low)
UART0_TXD
AB3
VDD33
O5
Async
UART0, UART transmit data output. The firmware only
outputs debug messages on this port.
UART0_RXD
AD1
VDD33
I4
Async
UART0, UART receive data input. The firmware does not
support receiving data on this port.
UART0_RTSZ
AD2
VDD33
O5
Async
UART0, UART ready to send hardware flow control output
(active low)
UART0_CTSZ
AE2
VDD33
I4
Async
UART0, UART clear to send hardware flow control input
(active low). This pin requires an external 10 kΩ pulldown
resistor.
USB_DAT_N (2)
USB_DAT_P
C5
D6
VDD33
B9
Async
USB D– I/O
USB D+ I/O
HOLD_BOOTZ
F24
VDD33
B2
Async
Boot mode. When this pin is held low, the firmware boots-
up in bootload mode. When pin is held high, the firmware
boots-up in normal operating mode. This pin requires an
external 1 kΩ pullup resistor.
USB_ENZ (2)
E25
VDD33
B2
Async
The firmware will use this pin to enable an external buffer
on the USB data lines after it has completed initialization.
FAULT_STATUS
AC11
VDD33
O2
Async
This signal toggles or held high to indicate status faults.
HEARTBEAT
AB12
VDD33
O2
Async
This signal toggles to indicate the system is operational.
Period is approximately 1 second.
SEQ_INT2
H26
VDD33
I2
Async
This signal serves as an interrupt for pattern sequencing
and must be connected to SEQ_AUX6.




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83 


Datasheet Download




Enlace URL

¿ALLDATASHEET es útil para Ud.?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl