KM732V789 datasheet(8/15 Pages) SAMSUNG

No. de pieza	KM732V789

Descripción Electrónicos	128Kx32 Synchronous SRAM

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Fabricante Electrónico	SAMSUNG [Samsung semiconductor]

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KM732V789

128Kx32 Synchronous SRAM

- 8 -

Rev 5.0

February 1999

AC TIMING CHARACTERISTICS(TA=0 to 70

°C, VDD=3.3V+0.3V/-0.165V)

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and

CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.

3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.

PARAMETER

SYMBOL

-60

-67

-72

-10

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle Time

tCYC

6.0

-

6.7

-

7.2

-

10.0

-

ns

Clock Access Time

tCD

-

3.5

-

3.8

-

4.0

-

4.5

ns

Output Enable to Data Valid

tOE

-

3.5

-

3.8

-

4.0

-

4.5

ns

Clock High to Output Low-Z

tLZC

0

-

0

-

0

-

0

-

ns

Output Hold from Clock High

tOH

1.5

-

1.5

-

1.5

-

1.5

-

ns

Output Enable Low to Output Low-Z

tLZOE

0

-

0

-

0

-

0

-

ns

Output Enable High to Output High-Z

tHZOE

-

3.5

-

3.5

-

3.8

-

4.0

ns

Clock High to Output High-Z

tHZC

1.5

6.0

1.5

6.7

1.5

7.2

1.5

9.0

ns

Clock High Pulse Width

tCH

2.4

-

2.6

-

2.8

-

3.4

-

ns

Clock Low Pulse Width

tCL

2.4

-

2.6

-

2.8

-

3.4

-

ns

Address Setup to Clock High

tAS

1.5

-

1.5

-

1.5

-

1.5

-

ns

Address Status Setup to Clock High

tSS

1.5

-

1.5

-

1.5

-

1.5

-

ns

Data Setup to Clock High

tDS

1.5

-

1.5

-

1.5

-

1.5

-

ns

Write Setup to Clock High (GW, BW, WEX)

tWS

1.5

-

1.5

-

1.5

-

1.5

-

ns

Address Advance Setup to Clock High

tADVS

1.5

-

1.5

-

1.5

-

1.5

-

ns

Chip Select Setup to Clock High

tCSS

1.5

-

1.5

-

1.5

-

1.5

-

ns

Address Hold from Clock High

tAH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Address Status Hold from Clock High

tSH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Data Hold from Clock High

tDH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Write Hold from Clock High (GW, BW, WEX)

tWH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Address Advance Hold from Clock High

tADVH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Chip Select Hold from Clock High

tCSH

0.5

-

0.5

-

0.5

-

0.5

-

ns

ZZ High to Power Down

tPDS

2

-

2

-

2

-

2

-

cycle

ZZ Low to Power Up

tPUS

2

-

2

-

2

-

2

-

cycle

Output Load(B)

(for tLZC, tLZOE, tHZOE & tHZC)

Dout

5pF*

Fig. 1

* Including Scope and Jig Capacitance

Output Load(A)

Dout

Z0=50

Ω

* Capacitive Load consists of all components of

30pF*

the test environment.

RL=50

Ω

353

Ω / 1538Ω

+3.3V for 3.3V I/O

319

Ω / 1667Ω

VL=1.5V for 3.3V I/O

VDDQ/2 for 2.5V I/O

/+2.5V for 2.5V I/O

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