MC10H124

http://onsemi.com

3

APPLICATIONS INFORMATION

The MC10H124 has TTL−compatible inputs and MECL

complementary open−emitter outputs that allow use as an

inverting/non−inverting translator or as a differential line

driver. When the common strobe input is at the low−logic

level, it forces all true outputs to a MECL low−logic state

and all inverting outputs to a MECL high−logic state.

An advantage of this device is that TTL−level information

can be transmitted differentially, via balanced twisted pair

lines, to MECL equipment, where the signal can be received

by the MC10H115 or MC10H116 differential line receivers.

The power supply requirements are ground, +5.0 V, and

−5.2 V.

ORDERING INFORMATION

Device

Package

MC10H124L

CDIP−16

25 Units/Rail

MC10H124P

PDIP−16

25 Units/Rail

MC10H124PG

PDIP−16

(Pb−Free)

25 Units/Rail

MC10H124FN

PLCC−20

46 Units/Rail

MC10H124FNG

PLCC−20

(Pb−Free)

46 Units/Rail

MC10H124FNR2

PLCC−20

1000 Tape & Reel

MC10H124M*

EIAJ−16

(Pb−Free)

50 Units/Rail

MC10H124MEL*

EIAJ−16

(Pb−Free)

2000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This device is manufactured with a Pb−Free external lead finish only.

Resource Reference of Application Notes

AN1405/D

− ECL Clock Distribution Techniques

AN1406/D

− Designing with PECL (ECL at +5.0 V)

AN1503/D

− ECLinPS

t I/O SPiCE Modeling Kit

AN1504/D

− Metastability and the ECLinPS Family

AN1568/D

− Interfacing Between LVDS and ECL

AN1642/D

− The ECL Translator Guide

AND8001/D

− Odd Number Counters Design

AND8002/D

− Marking and Date Codes

AND8020/D

− Termination of ECL Logic Devices

AND8066/D

− Interfacing with ECLinPS

AND8090/D

− AC Characteristics of ECL Devices