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CS7620 Datasheet(PDF) 8 Page - Cirrus Logic |
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CS7620 Datasheet(HTML) 8 Page - Cirrus Logic |
8 / 70 page CS7620 8 DS301PP2 2 GENERAL DESCRIPTION The CS7620 forms the heart of a four chip digital CCD Camera. The four chips include the CCD im- ager, the CS7620 CCD digitizer, a vertical drive in- terface chip and a backend DSP chip to further process the digital data (see Figure 4.) The CS7620 has a built-in timing generator which works with imagers from IBM and Polaroid. If other CCDs are used, the internal timing generator can be bypassed and replaced by an external device, which outputs the appropriate timing signals. The patented DRX technology allows the CS7620 to output data with 13-bit dynamic range, and at the same time reducing the power consumption to a 10- bit equivalent A/D converter. The digitized output is either available in 13-bits, 12-bits or 10-bits. The 10-bit output is created by companding the 13-bit A/D output to 10-bits. The companding curve consists of 4 linear segments, where each slope and each start point is user pro- grammable. Two output control signals and one output clock provide synchronization with the out- put data. A block diagram of the CS7620 chip is shown in Figure 5. CCD Vertical Drive DC-DC converter Backend DSP LCD Panel Video Output +5 V +5 V to -5 V CDS/ADC Timing Control CS7620 Figure 4. Digital Camera Block Diagram AIN RG H1 H2 H3 H4 CLOCK_IN BYPASS_PLL DIAG[1:0] DAC_OUT1 DAC_OUT2 SEN SDATI SDATO SCLK V1 V2 V3 V4 S1 S2 S3 S4 RD_OUT HSYNC EXPOSE LINE_ENA BG_RES REF_CAPN REF_CAPP TEST RST PWR_DN SCAN_MODE CLAMP CLKO DOUT[12:0] (up to 3 may be unused) GND[5] VDD[5] Σ CDS/VGA A/D Gain Adjust 13 to 10-bit Compander M U X Black Level Analog Clock Generator PLL DAC1 DAC2 Serial Interface Timing Generator Reference 1 µF 10 k Ω Figure 5. CS7620 Block Diagram |
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