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CS44800-CQZ Datasheet(PDF) 7 Page - Cirrus Logic |
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CS44800-CQZ Datasheet(HTML) 7 Page - Cirrus Logic |
7 / 81 page DS632PP1 7 CS44800 LIST OF TABLES Table 1. Common DAI_MCLK Frequencies.................................................................................. 25 Table 2. DAI Serial Audio Port Channel Allocations ..................................................................... 27 Table 3. Load Compensation Example Settings ........................................................................... 32 Table 4. Typical PWM Switch Rate Settings................................................................................. 34 Table 5. Digital Audio Interface Formats....................................................................................... 52 Table 6. Master Integer Volume Settings...................................................................................... 56 Table 7. Master Fractional Volume Settings ................................................................................. 57 Table 8. Channel Integer Volume Settings ................................................................................... 58 Table 9. Channel Fractional Volume Settings............................................................................... 59 Table 10. Limiter Attack Rate Settings..........................................................................................61 Table 11. Limiter Release Rate Settings....................................................................................... 61 Table 12. Channel Load Compensation Filter Coarse Adjust ....................................................... 62 Table 13. Channel Load Compensation Filter Fine Adjust............................................................ 62 Table 14. PWM Minimum Pulse Width Settings............................................................................ 69 Table 15. Differential Signal Delay Settings.................................................................................. 69 Table 16. Channel Delay Settings................................................................................................. 70 Table 17. Power Supply Sync Clock Divider Settings................................................................... 73 Table 18. Decimator Shift/Scale Coefficient Calculation Examples .............................................. 74 Table 19. Revision History ............................................................................................................ 80 |
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