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CS61584A-IQ5 Datasheet(PDF) 4 Page - Cirrus Logic |
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CS61584A-IQ5 Datasheet(HTML) 4 Page - Cirrus Logic |
4 / 54 page CS61584A 4 DS261PP5 DS261PP5 Table 13. CS61584A External Components..................................................................................... 48 Table 14. Quartz Crystal Specifications ........................................................................................... 50 Table 15. Suggested Quartz Crystals............................................................................................... 50 Table 16. Suggested Crystal Oscillators .......................................................................................... 50 Table 17. Transformer Specifications ............................................................................................... 51 Table 18. Recommended Transformers........................................................................................... 52 LIST OF FIGURES Figure 1. Signal Rise And Fall Characteristics .............................................................................. 9 Figure 2. Recovered Clock and Data Switching Characteristics ................................................... 9 Figure 3. Transmit Clock and Data Switching Characteristics ...................................................... 9 Figure 4. Serial Port Write Timing Diagram ................................................................................. 10 Figure 5. Serial Port Read Timing Diagram ................................................................................ 10 Figure 6. Parallel Port Timing - Motorola Mode ........................................................................... 12 Figure 7. Parallel Port Timing - Intel Read Mode ........................................................................ 12 Figure 8. Parallel Port Timing - Intel Write Mode ........................................................................ 12 Figure 9. Parallel Port Timing - Motorola Mode to RAM .............................................................. 13 Figure 10. Parallel Port Timing - Intel Read Mode from RAM or ROM ......................................... 13 Figure 11. Parallel Port Timing - Intel Write Mode to RAM ........................................................... 13 Figure 12. JTAG Switching Characteristics ................................................................................... 14 Figure 13. Examples of CS61584A Applications ........................................................................... 15 Figure 14. Typical Pulse Shape at DSX-1 Cross Connect ............................................................ 17 Figure 15. Mask of the Pulse at the 2048 kbps Interface .............................................................. 17 Figure 16. Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and jitter Attenuator) ............................................................................................................ 18 Figure 17. Typical Jitter Transfer Function .................................................................................... 19 Figure 18. Alarm Indication Event Relationships ........................................................................... 24 Figure 19. Phase Definition of Arbitrary Waveforms ..................................................................... 29 Figure 20. Example of Summing of Waveforms ............................................................................ 29 Figure 21. Serial Read/Write Format (SPOL = 0) .......................................................................... 30 Figure 22. Address Command byte ............................................................................................... 30 Figure 23. JTAG Circuitry Block Diagram ..................................................................................... 31 Figure 24. TAP Controller State Diagram ...................................................................................... 34 Figure 25. JTAG Instruction Register update ................................................................................ 37 Figure 26. JTAG Data Register update ......................................................................................... 38 Figure 27. Hardware Mode Configuration ..................................................................................... 48 Figure 28. Host Mode Serial Port Configuration ............................................................................ 49 Figure 29. Host Mode Parallel Port Configuration ......................................................................... 49 CS61584A 4 DS261F1 |
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