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TPA3100D2RGZR Datasheet(PDF) 2 Page - Texas Instruments

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No. de pieza TPA3100D2RGZR
Descripción Electrónicos  20-W STEREO CLASS-D AUDIO POWER AMPLIFIER
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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TPA3100D2RGZR Datasheet(HTML) 2 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
TYPICAL DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPA3100D2
SLOS469B – OCTOBER 2005 – REVISED OCTOBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC
Supply voltage
AVCC, PVCC
–0.3 V to 30 V
SHUTDOWN, MUTE
–0.3 V to VCC + 0.3 V
VI
Input voltage
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,
–0.3 V to VREG + 0.5 V
SYNC
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–40
°C to 85°C
TJ
Operating junction temperature range(2)
–40
°C to 150°C
Tstg
Storage temperature range
–65
°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
RLoad
Load Resistance
3.2
Ω Minimum
Human body model (3) (all pins)
±2 kV
Electrostatic discharge
Machine model (4) (all pins)
±200 V
Charged-device model (5) (all pins)
±500 V
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the TQFP thermal pad.
(3)
In accordance with JEDEC Standard 22, Test Method A114-B.
(4)
In accordance with JEDEC Standard 22, Test Method A115-A
(5)
In accordance with JEDEC Standard 22, Test Method C101-A
PACKAGE
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
48-pin QFN
4.7 W
37.7 mW/
°C(1)
3.02 W
2.45 W
48-pin TQFP
4.65 W
37.2 mW/
°C(2)
2.98 W
2.42 W
(1)
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about
using the QFN thermal pad.
(2)
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the TQFP
thermal pad.
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VCC
Supply voltage
PVCC, AVCC
10
26
V
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
VIH
High-level input voltage
2
V
SYNC
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
VIL
Low-level input voltage
0.8
V
SYNC
SHUTDOWN, VI = VCC, VCC = 24 V
125
MUTE, VI = VCC, VCC = 24 V
75
IIH
High-level input current
µA
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG,
2
VCC = 24 V
2


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