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CDCVF857RHAR Datasheet(PDF) 5 Page - Texas Instruments

No. de pieza CDCVF857RHAR
Descripción Electrónicos  2.5-V PHASE-LOCK LOOP CLOCK DRIVER
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Fabricante Electrónico  TI [Texas Instruments]
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CDCVF857RHAR Datasheet(HTML) 5 Page - Texas Instruments

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CDCVF857
2.5V PHASELOCK LOOP CLOCK DRIVER
SCAS047D − MARCH 2003 − REVISED JUNE 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
DGG
RHA/RTB
GQL
I/O
DESCRIPTION
AGND
17
9
H1
Ground for 2.5
-V analog supply
AVDD
16
8
G2
2.5
-V analog supply
CLK, CLK
13, 14
5, 6
F1, F2
I
Differential clock input
FBIN, FBIN
35, 36
25, 26
F5, F6
I
Feedback differential clock input
FBOUT, FBOUT
32, 33
21, 22
H6, G5
O
Feedback differential clock output
GND
1, 7, 8, 18, 24,
25, 31, 41, 42, 48
1, 10
A3, A4, C1, C2, C5,
C6, H2, H5, K3, K4
Ground
PWRDWN
37
27
E6
I
Output enable for Y and Y
VDDQ
4, 11, 12, 15, 21,
28, 34, 38, 45
4, 7, 13, 18, 23,
24, 28, 33, 38
B3, B4, E1, E2, E5,
G1, G6, J3, J4
2.5-V supply
Y0, Y0
3, 2
37, 36
A1, A2
O
Y1, Y1
5, 6
39, 40
B2, B1
O
Y2, Y2
10, 9
3, 2
D1, D2
O
Y3, Y3
20, 19
12,11
J2, J1
O
Y4, Y4
22, 23
14, 15
K1, K2
O
Buffered output copies of input clock, CLK, CLK
Y5, Y5
46, 47
34, 35
A6, A5
O
Buffered output copies of input clock, CLK, CLK
Y6, Y6
44, 43
32, 31
B5, B6
O
Y7, Y7
39, 40
29, 30
D6, D5
O
Y8, Y8
29, 30
19, 20
J5, J6
O
Y9, Y9
27, 26
17, 16
K6, K5
O
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VDDQ, AVDD
0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Notes 1 and 2)
0.5 V to VDDQ + 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2)
0.5 V to VDDQ + 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VDDQ)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VDDQ)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VDDQ)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current to GND or VDDQ
±100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range Tstg
65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
qJA For TSSOP (DGG) Package (see Note 3)
qJA For MLF (RHA/RTB) Package
qJA For BGA(GQL) Package (see Note 4)
Airflow
Low K
High K
Airflow
With 4 Thermal Vias
Airflow
High K
0 ft/min
89.1
°C/W
70
°C/W
0 ft/min
44.7
°C/W
0 ft/min
132.2
°C/W
150 ft/min
78.5
°C/W
65.3
°C/W
150 ft/min
150 ft/min
126.4
°C/W
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4. Connecting the NC-balls (C3, C4, D3, D4, G3, G4, H3, H4) to a ground plane improves the
θJA to 114.8°C/W (0 airflow).


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