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STK14C88-M
April 1999
5-47
HARDWARE MODE SELECTION
Note m: HSB store operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the store (if any) completes, the part
will go into standby mode, inhibiting all operations until HSB rises.
Note n:
The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note o:
While there are 15 addresses on the STK14C88-M, only the lower 14 are used to control software modes.
Note p:
I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE
STORE CYCLE
(VCC = 5.0V ± 10%)
e
Note q:
E and G low and W high for output behavior.
Note r:
tRECOVER is only applicable after tSTORE is complete.
HARDWARE
STORE CYCLE
E
W
HSB
A13 - A0 (hex)
MODE
I/O
POWER
NOTES
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
p
L
L
H
X
Write SRAM
Input Data
Active
X
X
L
X
Nonvolatile
STORE
Output High Z
lCC2
m
LH
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
lCC2
n, o, p
LH
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
n, o, p
NO.
SYMBOLS
PARAMETER
STK14C88-M
UNITS
NOTES
Standard
Alternate
MIN
MAX
22
tSTORE
tHLHZ
STORE Cycle Duration
10
ms
i, q
23
tDELAY
tHLQZ
Time Allowed to Complete SRAM Cycle
1
µs
i, q
24
tRECOVER
tHHQX
Hardware
STORE High to Inhibit Off
700
ns
q, r
25
tHLHX
Hardware
STORE Pulse Width
20
ns
26
tHLBL
Hardware
STORE Low to STORE Busy
300
ns
DATA VALID
HSB (IN)
DQ (DATA OUT)
DATA VALID
25
tHLHX
23
tDELAY
22
tSTORE
24
tRECOVER
HSB (OUT)
HIGH IMPEDANCE
26
tHLBL
HIGH IMPEDANCE