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SM532 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

No. de pieza SM532
Descripción Electrónicos  Low EMI Spectrum Spread Clock
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Fabricante Electrónico  ETC1 [List of Unclassifed Manufacturers]
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SM532 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

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YJGP VKOKPI KU ETKVKECN
YJGP VKOKPI KU ETKVKECN
SM532
Approved Product
Low EMI Sprectum Spread Clock
International Microcircuits,Inc.
8/31/98
525 Los Coches St., Milpitas, 95035 408-263-6300, FAX 408-263-6571
Rev. 1.4
http:/www.imicorp.com
Page 3 of 14
Figure 2. SOIC Package Pin Assignment
Pin Descriptions
Pin No.
Pin Name
I/O
TYPE
Description
1,2
OSCin,
OSCout
I/O
CMOS
Pins form an on-chip reference oscillator when connected to terminals
of an external parallel resonant crystal. OSCin may be connected to a
TTL/CMOS external clock source. AC coupling may be required. If
OSCin is connected to an external clock other than a crystal, leave
OSCout (pin 2) unconnected. The input frequency range is 14 to 120
Mhz @ 5.0 VDC.
3
AVDD
Power
Analog circuit positive power supply.
4, 7
S0, S1
I
TTL
Input control used to select the frequency multiplication at Fout,
relative to the reference clock. See table on page 5.
S0 has internal pull-down resistor, S1 has internal pull-up resistor.
5
LF
O
Analog
Single ended tri-state output of the phase detector.
A two pole
passive loop filter is connected to LF. See table on page 7 for proper
values.
6
AVSS
Ground
Ground
Analog circuit ground.
8
SSON
I
TTL
Input control pin used to enable modulation at the Fout pin.
SSON = 0 = Modulation ON. (default)
SSON = 1 = Modulation OFF.
Has internal pull-down resistor.
9, 11
S3, S2
I
TTL
Input control pins used to set the amount of modulation at Fout. See
table on page 6 for settings. S2 has internal pull-up resistor, S3 has
internal pull-down resistor.
10, 16
DVDD
Power
Power
Digital positive power supply. Should be kept separate from analog
power for best performance.
12
Fout
O
TTL
Modulated clock output.
13, 14
R1, R0
I
TTL
Input pins control the input frequency range as described in table on
page 5.
R0 and R1 have internal pull-up resistor.
15
DVSS
Ground
Ground
Digital Circuit Ground
Table 1.
1
2
3
4
5
6
7
89
10
16
15
14
13
12
11
OSCin
OSCout
AVDD
S0
LF
AVSS
S1
SSON
DVDD
DVSS
R0
R1
Fout
S2
S3
DVDD
SM532


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