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KM416S1021C Datasheet(PDF) 6 Page - Samsung semiconductor

No. de pieza KM416S1021C
Descripción Electrónicos  512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
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Fabricante Electrónico  SAMSUNG [Samsung semiconductor]
Página de inicio  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM416S1021C Datasheet(HTML) 6 Page - Samsung semiconductor

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KM416S1021C
REV. 1. May '98
CMOS SDRAM
Preliminary
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
-7
-S
-8
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
tCC
7
1000
-
1000
8
1000
ns
1
CAS latency=2
12
10
13
CLK to Valid
Output Delay
CAS latency=3
tSAC
5.5
-
6
ns
1,2
CAS latency=2
7
6
8
Output data hold time
tOH
2.5
2
2.5
ns
2
CLK high pulse width
tCH
3
3.5
3
ns
3
CLK low pulse width
tCL
3
3.5
3
ns
3
Input setup time
tSS
2
2
2.5
ns
3
Input hold time
tSH
1
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
tSHZ
5.5
-
6
ns
CAS latency=2
7
8
8
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :


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