TC59LM806CFT-50 datasheet(10/38 Pages) TOSHIBA

No. de pieza	TC59LM806CFT-50

Descripción Electrónicos	4,194,304 / 8,388,608-WORDS x 4 BANKS x 16 / 8-BITS Network FCRAM

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Fabricante Electrónico	TOSHIBA [Toshiba Semiconductor]

Página de inicio	http://www.semicon.toshiba.co.jp/eng

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10 / 38 page

TC59LM814/06CFT-50,-55,-60

2002-08-19

10/38

POWER UP SEQUENCE

(1)

As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.

(2)

Apply VDD before or at the same time as VDDQ.

(3)

Apply VDDQ before or at the same time as VREF.

(4)

Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).

(5)

After stable power and clock, apply DESL and take PD =H.

(6)

Issue EMRS to enable DLL and to define driver strength. (Note: 1)

(7)

Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)

(8)

Issue two or more Auto-Refresh commands (Note: 1).

(9)

Ready for normal operation after 200 clocks from Extended Mode Register programming.

Note:

(1)

Sequence 6, 7 and 8 can be issued in random order.

(2)

L = Logic Low, H = Logic High

CLK

Command

DQ

Address

VDD

VDDQ

VREF

CLK

PD

2.5V(TYP)

1.25V(TYP)

200 us(min)

tPDEX

lPDA

lRSC

lREFC

200clock cycle(min)

DESL

RDA

DESL

RDA MRS

DESL WRA REF

DESL

WRA REF

DESL

op-code

EMRS

op-code

MRS

Hi-Z

DQS

EMRS

MRS

Auto Refresh cycle

Normal Operation

MRS

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TC59LM806CFT-50 Datasheet(PDF) 10 Page - Toshiba Semiconductor

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