SN74LS194A

http://onsemi.com

5

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Clock or MR Pulse Width

20

ns

Mode Control Setup Time

30

ns

Data Setup Time

20

ns

Hold time, Any Input

0

ns

Recovery Time

25

ns

DEFINITIONS OF TERMS

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW to HIGH in

order to be recognized and transferred to the outputs.

following the clock transition from LOW to HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW to HIGH and still be recognized.

required between the end of the reset pulse and the clock

transition from LOW to HIGH in order to recognize and

transfer HIGH Data to the Q outputs.

AC WAVEFORMS

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays Clock Pulse

Figure 2. Master Reset Pulse Width, Master Reset

to Output Delay and Master Reset to Clock

Recovery Time

1.3 V

1.3 V

OTHER CONDITIONS: MR = H

OTHER CONDITIONS: MR = H

CLOCK

OUTPUT*

(––– IS SHIFT LEFT)

CLOCK

CLOCK

CLOCK

OUTPUT

OUTPUT

(STABLE TIME)

1/fmax

MR

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V