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SN74LS194 Datasheet(PDF) 5 Page - ON Semiconductor |
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SN74LS194 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 8 page SN74LS194A http://onsemi.com 5 AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions tW Clock or MR Pulse Width 20 ns ts Mode Control Setup Time 30 ns ts Data Setup Time 20 ns VCC = 5.0 V th Hold time, Any Input 0 ns trec Recovery Time 25 ns DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 1. Clock to Output Delays Clock Pulse Width and fmax Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time 1.3 V 1.3 V OTHER CONDITIONS: S1 = L, MR = H, S0 = H OTHER CONDITIONS: S0, S1 = H OTHER CONDITIONS: PO = P1 = P2 = P3 = H OTHER CONDITIONS: MR = H OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY OTHER CONDITIONS: MR = H S0 S1 DSR DSL P0 P1 P2 P3 CLOCK OUTPUT* (––– IS SHIFT LEFT) CLOCK CLOCK CLOCK OUTPUT OUTPUT S0 S1 ts(H) th(L) = 0 th(H) = 0 th(H) = 0 ts(H) th(L) = 0 ts(L) th = 0 th = 0 (STABLE TIME) tPHL tPLH 1/fmax tW ts(L) MR tW trec tPHL 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V ts ts Figure 3. Setup (ts) and Hold (th) Time for Serial Data (DSR, DSL) and Parallel Data (P0, P1, P2, P3) Figure 4. Setup (ts) and Hold (th) Time for S Input |
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