SN74LS253

http://onsemi.com

3

LOGIC DIAGRAM

14

1

26

7

3

4

5

9

11

13

10

12

15

GND = PIN 8

= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The LS253 contains two identical 4-Input Multiplexers

with 3-state outputs. They select two bits from four sources

inputs which when HIGH, forces the outputs to a high

impedance (high Z) state.

The LS253 is the logic implementation of a 2-pole,

4-position switch, where the position of the switch is

determined by the logic levels supplied to the two select

inputs. The logic equations for the outputs are shown below:

If the outputs of 3-state devices are tied together, all but

one device must be in the high impedance state to avoid high

currents that would exceed the maximum ratings. Designers

should ensure that Output Enable signals to 3-state devices

whose outputs are tied together are designed so that there is

no overlap.

TRUTH TABLE

SELECT

INPUTS

DATA INPUTS

OUTPUT

ENABLE

OUTPUT

Z

X

X

X

X

X

X

H

(Z)

L

LL

XX

X

L

L

L

LH

XX

X

L

H

H

LX

LX

X

L

L

H

LX

HX

X

L

H

L

HX

XL

X

L

L

L

HX

XH

X

L

H

H

HX

XX

L

L

L

H

H

X

X

X

H

L

H

H = HIGH Level

L = LOW Level

X = Irrelevant

(Z) = High Impedance (off)