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SN74LS670 Datasheet(PDF) 2 Page - ON Semiconductor |
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SN74LS670 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page SN74LS670 http://onsemi.com 2 CONNECTION DIAGRAM DIP (TOP VIEW) Data Inputs Write Address Inputs Write Enable (Active LOW) Input Read Address Inputs Read Enable (Active LOW) Input Outputs D1 – D4 WA, WB EW RA, RB ER Q1 – Q4 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 1.5 U.L. 65 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.75 U.L. 15 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES LOGIC SYMBOL NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 13 12 11 10 9 1234 5 6 7 16 15 8 VCC D2 D1 WA WB EW Q1 ER Q2 D3 D4 RB RA Q4 Q3 GND VCC = PIN 16 GND = PIN 8 14 13 5 4 12 15 1 2 3 11 10 9 7 6 WA WB RA RB EW ER D1 D2 D3 D4 Q1 Q2 Q3 Q4 |
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