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TPS2110APW Datasheet(PDF) 6 Page - Texas Instruments |
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TPS2110APW Datasheet(HTML) 6 Page - Texas Instruments |
6 / 20 page TPS2110A TPS2111A SBVS043 − MARCH 2004 www.ti.com 6 TRUTH TABLE D1 D0 VI(VSNS) > 0.8V VI(IN2) > VI(IN1) OUT(1) 0 0 X X IN2 0 1 YES X IN1 0 1 NO NO IN1 0 1 NO YES IN2 1 0 X X IN1 1 1 X X Hi-Z X = Don’t care. (1)The under-voltage lockout circuit causes the output to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if neither of the supplies exceeds the internal VDD UVLO. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION D0 1 I TTL- and CMOS-compatible input pins. Each pin has a 1- µA pull-up. The truth table shown above illustrates the functionality of D0 and D1. D1 2 I TTL- and CMOS-compatible input pins. Each pin has a 1- µA pull-up. The truth table shown above illustrates the functionality of D0 and D1. GND 5 I Ground IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. ILIM 4 I A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2110A and TPS2111A, respectively. OUT 7 O Power switch output VSNS 3 I In the auto-switching mode (D0 = 1, D1 = 0), an internal power FET connects OUT to IN1 if the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT to the higher of IN1 and IN2. The truth table shown above illustrates the functionality of VSNS. |
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