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CDC950 Datasheet(PDF) 10 Page - Texas Instruments |
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CDC950 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 16 page CDC950 133MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) HCLK/HCLK (Type X1), CL = 2 pF, Rref = 475 Ω, 6 x Rref PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HCLK clock period‡ f(HCLK) = 100 MHz 10 10.2 ns HCLK clock period‡ f(HCLK) = 133 MHz 7.5 7.65 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz SSC off −80 80 ps Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz SSC on −110 110 ps tdc Duty cycle f(HCLK) = 100 or 133 MHz, Crossing point 45% 55% tsk(o) HCLK bus skew f(HCLK) = 100 or 133 MHz, Crossing point 70 ps tr Rise time† 0.7-V amplitude VO = 0.14 V to 0.56 V 175 700 ps tf Fall time† 0.7-V amplitude VO = 0.14 V to 0.56 V 175 700 ps v(cross) Cross point voltages† 0.7-V amplitude f(HCLK) = 100 or 133-MHz HCLK and HCLK 45% VOH 55% VOH V † These parameters are assured by design and lab characterization, not 100% production tested. ‡ The average over any 1-µs period of time is greater than the minimum specified period. CLK33 (Type 5), CL = 30 pF, RL = 500 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCI clock period† f(HCLK) = 100 or 133 MHz 30 30.06 30.6 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −150 150 ps t(dc) Duty cycle f(CLK33) = 33.3 MHz 45% 55% tr Rise time VO = 0.4 V to 2.4 V 0.5 2 ns tf Fall time VO = 0.4 V to 2.4 V 0.5 2 ns † The average over any 1-µs period of time is greater than the minimum specified period. 3V48 (Type 3), CL = 20 pF, RL = 500 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3V48 clock period f(HCLK) = 100 or 133 MHz 20.83 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −300 300 ps tdc Duty cycle f(3V48) = 48 MHz 45% 55% tr Rise time VO = 0.4 V to 2.4 V 1 4 ns tf Fall time VO = 0.4 V to 2.4 V 1 4 ns REF (Type 3), CL = 20 pF, RL = 500 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REF clock period f(REF) = 14.318 MHz 69.84 ns Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −0.5 0.5 ns t(dc) Duty cycle f(REF) = 14.318 MHz 45% 55% tr Rise time VO = 0.4 V to 2.4 V 1 4 ns tf Fall time VO = 0.4 V to 2.4 V 1 4 ns |
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