TC9WMB1FK,TC9WMB2FK

2002-07-31

4

3. Acknowledge

Data is transmitted and received in 8-bit units. The receiver sends an acknowledge signal by outputting a

low on SDA in the 9th clock cycle, indicating that it has received data normally. The transmitter releases

the bus in the 9th clock cycle to receive an acknowledge signal.

During a write, the chip is always the receiver so that it outputs an acknowledge signal each time it has

received eight bits of data.

During a read, the chip outputs an acknowledge signal after it receives an address following a start

condition. Then, it outputs read data and releases the bus to wait for an acknowledge signal from the

master. When it detects an acknowledge signal, it outputs data at the next address if it does not detect a

stop condition. If the chip does not detect an acknowledge signal, it stops read operation, and enters the

standby state when a stop condition occurs subsequently.

If the chip does not detect an acknowledge signal nor a stop condition, it keeps the bus released.

4. Device Addressing

After a start condition occurs, a 7-bit device address and a 1-bit read/write instruction code are input to

the chip.

The upper four bits are called device code, which must always be “1010”. The next three bits are used to

select a device on the bus. These three bits are not specified for this IC and can be set to any value.

The least significant bit (

W

R/

:

WRITE

READ/

) indicates a read instruction when set to 1 and a write

instruction when set to 0.

An instruction is not executed if the device address does not match the specified value.

Figure 4

MSD

1

0

1

0

×

×

×

W

/

R

LSB

×: Don’t care

Device code

Device address

Read/write instruction

code

Figure 3

SCL

SDA

Acknowledge output

1

8

9

SDA

Start condition