GS88218/36BB/D-333/300/250/200/150

512K x 18, 256K x 36

9Mb SCD/DCD Sync Burst SRAMs

333 MHz–150 MHz

2.5 V or 3.3 V I/O

119- and 165-Bump BGA

Commercial Temp

Industrial Temp

Rev: 1.02 10/2004

1/37

© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 165-bump BGA packages

Functional Description

Applications

The GS88218/36B is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

Register.

SCD and DCD Pipelined Reads

The GS88218/36B is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the

SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ

low) for multi-drop bus applications and normal drive strength

(ZQ floating or high) point-to-point applications. See the

Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88218/36B operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output

internal circuits and are 3.3 V and 2.5 V compatible.

Paramter Synopsis

-333

-300

-250

-200

-150

Unit

Pipeline

3-1-1-1

tCycle

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

ns

ns

Curr (x18)

Curr (x32/x36)

250

290

230

265

200

230

170

195

140

160

mA

mA

Flow Through

2-1-1-1

tCycle

4.5

4.5

5.0

5.0

5.5

5.5

6.5

6.5

7.5

7.5

ns

ns

Curr (x18)

Curr (x32/x36)

200

230

185

210

160

185

140

160

128

145

mA

mA