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LM27964SQ-I Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LM27964SQ-I Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 13 page  Circuit Description OVERVIEW The LM27964 is a white LED driver system based upon an adaptive 1.5x/1x CMOS charge pump capable of supplying up to 180mA of total output current. With three separately controlled banks of constant current sinks, the LM27964 is an ideal solution for platforms requiring a single white LED driver for main and sub displays, as well as other general purpose lighting needs. The tightly matched current sinks ensure uniform brightness from the LEDs across the entire small-format display. Each LED is configured in a common anode configuration, with the peak drive current being programmed through the use of external R SETx resistors. An I 2C compatible interface is used to enable and vary the brightness within the indi- vidual current sink banks. For BankA and BankB, 16 levels of PWM brightness control are available, while 4 analog levels are present for the DKEY driver. CIRCUIT COMPONENTS Charge Pump The input to the 1.5x/1x charge pump is connected to the V IN pin, and the regulated output of the charge pump is con- nected to the V OUT pin. The recommended input voltage range of the LM27964 is 3.0V to 5.5V. The device’s regu- lated charge pump has both open loop and closed loop modes of operation. When the device is in open loop, the voltage at V OUT is equal to the gain times the voltage at the input. When the device is in closed loop, the voltage at V OUT is regulated to 4.6V (typ.). The charge pump gain transitions are actively selected to maintain regulation based on LED forward voltage and load requirements. This allows the charge pump to stay in the most efficient gain (1x) over as much of the input voltage range as possible, reducing the power consumed from the battery. LED Forward Voltage Monitoring The LM27964 has the ability to switch converter gains (1x or 3/2x) based on the forward voltage of the LED load. This ability to switch gains maximizes efficiency for a given load. Forward voltage monitoring occurs on all diode pins within BankA and BankB (DKEY is not monitored). At higher input voltages, the LM27964 will operate in pass mode, allowing the POUT voltage to track the input voltage. As the input voltage drops, the voltage on the DXX pins will also drop (V DXX =VPOUT –VLEDx). Once any of the active Dxx pins reaches a voltage approximately equal to 375mV, the charge pump will then switch to the gain of 3/2. This switchover ensures that the current through the LEDs never becomes pinched off due to a lack of headroom on the current sources. Only active Dxx pins will be monitored. For example, if only BankA is enabled, the LEDs in BankB will not affect the gain transition point. If both banks are enabled, all diodes will be monitored, and the gain transition will be based upon the diode with the highest forward voltage. The DKEY pin is not monitored as it is intended to be for keypad LEDs. Keypad LEDs generally require lower current, resulting in lower for- ward voltage compared to the BankA and BankB LEDs that have higher currents. In the event that only the DKEY driver is enabled without either BankA or BankB, the charge pump will default to 3/2 mode to ensure the DKEY driver has enough headroom. It is not recommended that any of the BankA or BankB drivers be left disconnected if either bank will be used in the application. If Dxx pin/s are left unconnected, the LM27964 will default to the gain of 3/2. If the BankA or BankB drivers are not going to be used in the application, leaving the Dxx pins is acceptable as long as the ENx bit in the general purpose register is set to "0". I 2C Compatible Interface DATA VALIDITY The data on SDIO line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. A pull-up resistor between VIO and SDIO must be greater than [ (VIO-V OL) / 2mA] to meet the VOL requirement on SDIO. Using a larger pull-up resistor results in lower switch- ing current with slower edges, while using a smaller pull-up results in higher switching currents with faster edges. START AND STOP CONDITIONS START and STOP conditions classify the beginning and the end of the I 2C session. A START condition is defined as SDIO signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDIO transition- ing from LOW to HIGH while SCL is HIGH. The I 2C master always generates START and STOP conditions. The I 2C bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the I 2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. The data on SDIO line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when CLK is LOW. TRANSFERING DATA Every byte put on the SDIO line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. 20138106 FIGURE 1. Data Validity Diagram 20138111 FIGURE 2. Start and Stop Conditions www.national.com 8 |
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