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DMA2275 Datasheet(PDF) 9 Page - Micronas |
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DMA2275 Datasheet(HTML) 9 Page - Micronas |
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9 / 48 page  DMA 2275, DMA 2286 9 6. Sound Processor The DMA 2286 contains an additional sound processor, which is loaded via the data burst input. The sound pro- cessor consists of: – spectrum descrambler – deinterleaver – sound processing – S Bus interface These blocks are identical to the sound processing blocks of the DMA 2281 (see ref. 2). Both sound proces- sors are able to decode 4 sound channels out of one single subframe. The subframe position is program- mable to allow full channel data reception. On the DMA 2286 the output of the deinterleaver is inter- nally fed to the packet descrambler and the des- crambled packets are going back to the sound proces- sor. The sound processor needs a separate external 64 k x 1 bit DRAM, which is independent from the acqui- sition DRAM and is not accessible by software. 6.1. The S Bus Interface and the S Bus The S bus has been designed to connect the digital sound output of the DMA 2271 or DMA 2281 MAC De- coder or the MSP 2400 NICAM Demodulator/Decoder to audio–processing ICs such as the AMU 2481 Audio Mix- er or the ACP 2371 Audio Processor etc., and to connect these ICs one to the other. The S bus is a unidirectional, digital bus which transmits the sound information in one direction only, so that it is not necessary to solve priority problems on the bus. The S bus consists of the three lines: S–Clock, S–Ident, and S–Data. The DMA 2271, DMA 2281 or the MSP 2400 generates the signals S–Clock and S–Ident, which control the data transfer to and between the various pro- cessors which follow the DMA 2271, DMA 2281 or the MSP 2400. For this, the S–Clock and S–Ident inputs of all processors in the system are connected to the S– Clock and S–Ident outputs of the DMA 2271, DMA 2281 or the MSP 2400. S–Data output of the DMA 2271, DMA 2281 or MSP 2400 is connected to the S–Data input of the next following AMU, the AMU’s S–Data output is connected to the ACP’s S–Data input and so on. The sound information is transmitted in frames of 64 bits, divided into four successive 16–bit samples. Each sam- ple represents one sound channel. The timing of a com- plete transmission of four samples is shown in Fig. 9–13, the times are specified under “Recommended Operat- ing Conditions”. The transmission starts with the LSB of the first sample. The S–Clock signal is used to write the data into the receiver’s input register. the S–Ident signal marks the end of one frame of 64 bits and is used as latch pulse for the input register. The repetition rate of S–Ident pulses is identical to the sampling rate of the D/D2–MAC or NICAM sound signal; thus it is possible to transfer four sound channels simultaneously. The S bus interface of the DMA 2286 mainly consists of an output register, 64–bit wide. The timing to write bit by bit is supplied by the Audio–Clock signal. In the case of an S–Ident pulse, the contents of the output register are written to the S–Data output. The S_Bus_Data line of the DMA 2286 can be con- nected to that of the DMA 2281 if only one audio proces- sor AMU 2481 is available. In this case each S_Bus channel of both DMA chips can be enabled or disabled under software control. |
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