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DAC667 Datasheet(PDF) 3 Page - Burr-Brown (TI) |
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DAC667 Datasheet(HTML) 3 Page - Burr-Brown (TI) |
3 / 9 page 3 ® DAC667 TIMING SPECIFICATIONS SYMBOL PARAMETER MIN TYP MAX UNITS tDC Data Valid to End of CS 50 – – ns tAC Address Valid to End of CS 100 – – ns tCP CS Pulse Width 100 – – ns tDH Data Hold Time 0 – – ns tSETT Output Voltage Settling Time – 2 4 µs All models, TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V. ABSOLUTE MAXIMUM RATINGS VCC to Power Ground .............................................................. 0V to +18V VEE to Power Ground .............................................................. 0V to –18V Digital Inputs (Pins 11–15, 17–28) to Power Ground ............. –1V to +7V Ref In to Reference Ground .............................................................. ±12V Bipolar Offset to Reference Ground ................................................. ±12V 10V Span Resistor to Reference Ground ......................................... ±12V 20V Span Resistor to Reference Ground ......................................... ±24V Ref Out, VOUT (Pins 6, 9) .................... Indefinite Short to Power Ground, Momentary Short To VCC Power Dissipation ........................................................................ 1000mW ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION TEMPERATURE LINEARITY ERROR GAIN TC, max PACKAGE DRAWING PRODUCT PACKAGE RANGE max at 25 °C (ppm/ °C) NUMBER(1) DAC667JP 28-Pin Plastic DIP 0 °C to +70°C ±1/2LSB ±30 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. TIMING DIAGRAMS Load first rank from Data Bus; A3 = 1. t Write Cycle #1 t SETT CS ±1/2LSB A3 t AC t CP Load second rank from first rank; A2, A1, A0 = 1. Write Cycle #2 Output CS A2–A0 t AC t DC t DH t CP DB11–DB0 |
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