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Si5600
Preliminary Rev. 0.31
9
Table 5. AC Characteristics (Receiver PLL)
(VDD = 1.8 V ± 5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
JTOL(PP)
f = 2.4 kHz
15
30
—
UIpp
f = 24 kHz
1.5
3.0
—
UIpp
f = 400 kHz
1.5
3.0
—
UIpp
f = 4 MHz
0.15
0.3
—
UIpp
Acquisition Time
TAQ
——
20
µs
Input Reference Clock Frequency
RCFREQ
REFRATE = 1
—
622
667
MHz
REFRATE = 0
—
155
167
MHz
Reference Clock Duty Cycle
RCDUTY
40
50
60
%
Reference Clock Frequency
Tolerance
RCTOL
–100
—
100
ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)
LOL
TBD
600
1000
ppm
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)
LOCK
TBD
300
TBD
ppm
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
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