Agere Systems Inc.

7

Data Sheet

January 2005

One-Cable Transceiver/Arbiter Device

FW801BF PHY 1394a-2000

Signal Information

Table 2. Signal Descriptions

Ball

Number

Signal*

Type

Name/Description

G4

C_LKON

I/O

Bus Manager Capable Input and Link-On Output. On hardware reset

(RESETN), this ball is used to set the default value of the contender status

indicated during self-ID. The bit value programming is done by tying the

signal through a 10 k

GND (low, not bus manager capable). Using either the pull-up or pull-

down resistor allows the link-on output to override the input value when

necessary.

After hardware reset, this ball is set as an output. If the LPS is inactive,

C_LKON indicates one of the following events by asserting a 6.114 MHz

signal.

1. FW801BF receives a link-on packet addressed to this node.

2. Port_event register bit is 1.

3. Any of the Timeout, Pwr_fail, or Loop register bits are 1 and the

Watchdog register bit is also 1.

4. Once activated, the C_LKON output will continue active until the LPS

becomes active. The PHY also deasserts the C_LKON output when a

1394 bus reset occurs, if the C_LKON is active due solely to the recep-

tion of a link-on packet.

Note: If an interrupt condition exists that would otherwise cause the

C_LKON output to be activated if the LPS were inactive, the

C_LKON output will be activated when the LPS subsequently

becomes inactive.

H1

CNA

O

Cable-Not-Active Output. CNA is asserted high when none of the PHY

ports are receiving an incoming bias voltage. This circuit remains active

during the powerdown mode.

H5

CPS

I

Cable Power Status. CPS is normally connected to the cable power

through a 400 k

Ω resistor. This circuit drives an internal comparator that

detects the presence of cable power. This information is maintained in one

internal register and is available to the LLC by way of a register read (see

or source 1394 power (VP), this ball can be tied to ground.

be set.

A1

CTL[0]

I/O

Control I/O. The CTLn signals are bidirectional communications control

signals between the PHY and the LLC. These signals control the passage

of information between the two devices. Bus-keeper circuitry is built into

these terminals.

B1

CTL[1]

C1, C2, D1,

E1, E2, F1,

F2, G2

D[0:7]

I/O

Data I/O. The Dn signals are bidirectional and pass data between the PHY

and the LLC. Bus-keeper circuitry is built into these terminals.

* Active-low signals are indicated by “N” at the end of signal names, within this document.