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GS8162Z72C-200I Datasheet(PDF) 3 Page - GSI Technology |
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GS8162Z72C-200I Datasheet(HTML) 3 Page - GSI Technology |
3 / 31 page GS8162Z72 BGA Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD DQE DQF DQG DQH I/O Data Input and Output pins BA, BB, BC,BD, BE, BF, BG,BH I Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low NC — No Connect CK I Clock Input Signal; active high W I Write Enable. Writes all enabled bytes; active low E1, E3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low MCH I Must Connect High MCL Must Connect Low PE I Parity Bit Enable; active low (High = x64 Mode, Low = x72 Mode) ADV I Burst Address Counter Advance Enable; active high ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply GS8162Z72C Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.22 11/2005 3/31 © 1999, GSI Technology |
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