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GS8170DD36C-250I Datasheet(PDF) 10 Page - GSI Technology |
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GS8170DD36C-250I Datasheet(HTML) 10 Page - GSI Technology |
10 / 29 page GS8170DD36C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 10/29 © 2002, GSI Technology, Inc. It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the Echo Clocks. In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2 would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed. Echo Clock Control in Two Banks of Double Data Rate SigmaRAMs QA0 QA1 QC0 QC1 QB0 QB1 QD0 QD1 Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false. CQ1 + CQ2 Read Read DQ Bank 2 CQ Bank 2 CQ Bank 1 Read DQ Bank 1 Address A B ADV Read Read F /E2 Bank 1 E2 Bank 2 CDE CK |
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