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GS8182S18D-167I Datasheet(PDF) 5 Page - GSI Technology |
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GS8182S18D-167I Datasheet(HTML) 5 Page - GSI Technology |
5 / 31 page GS8182S18D-267/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.08a 8/2005 5/31 © 2003, GSI Technology Burst of 2 SigmaSIO-II SRAM DDR Write The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K. SigmaSIO-II Double Data Rate SRAM Write First Write A Read B NOP Read C Write D NOP Read E Read F NOP A B C D E F A A+1 D D+1 A A+1 D D+1 B B+1 C C+1 E E+1 F K K Address LD R/W BWx D C C Q CQ CQ |
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