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GS8170LW72AGC-350 Datasheet(PDF) 5 Page - GSI Technology

No. de pieza GS8170LW72AGC-350
Descripción Electrónicos  18Mb 誇1x1Lp CMOS I/O Late Write SigmaRAM
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Fabricante Electrónico  GSI [GSI Technology]
Página de inicio  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8170LW72AGC-350 Datasheet(HTML) 5 Page - GSI Technology

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GS8170LW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
5/32
© 2003, GSI Technology
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Single Data Rate Pipelined Read
F
D
Address
Read
CK
E
QC
QD
CQ
Read
Deselect
Read
Read
AXX
C
Key
Hi-Z
Access
ADV
QA
/E1
/W
DQ


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