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74ALS74ADB Datasheet(PDF) 2 Page - NXP Semiconductors |
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74ALS74ADB Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74ALS74A Dual D-type flip-flop with set and reset 2 1996 Jul 01 853–1278 01670 DESCRIPTION The 74ALS74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock input. When set and reset are inactive (High), data at the D input is transferred to the Q and Q outputs on the Low-to-High transition of the clock. Data must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74ALS74A 150MHz 3.0mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 14-pin plastic DIP 74ALS74AN SOT27-1 14-pin plastic SO 74ALS74AD SOT108-1 14-pin plastic SSOP Type II 74ALS74ADB SOT337-1 PIN CONFIGURATION 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND VCC SD1 Q1 Q1 CP1 RD1 D1 RD0 D0 Q0 CP0 SD0 Q0 SF00045 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0, D1 Data inputs 1.0/2.0 20 µA/0.2mA CP0, CP1 Clock inputs (active rising edge) 1.0/2.0 20 µA/0.2mA SD0, SD1 Set inputs (active-Low) 2.0/4.0 40 µA/0.4mA RD0, RD1 Reset inputs (active-Low) 2.0/4.0 40 µA/0.4mA Q0, Q1, Q0, Q1 Data outputs 20/80 0.4mA/8mA NOTE: One (1.0) ALS unit load is defined as: 20 µA in the High state and 0.1mA in the Low state. LOGIC SYMBOL Q0 Q0 Q1 Q1 56 98 VCC = Pin 14 GND = Pin 7 3 4 1 11 10 13 CP0 SD0 RD0 CP1 SD1 RD1 D0 D1 212 SF00046 IEC/IEEE SYMBOL 4 3 2 1 10 11 12 13 5 6 9 8 & S S C1 C2 R 1D 2D R SF00047 |
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