74HC259PW datasheet(11/11 Pages) PHILIPS

11 / 11 page

December 1990

11

Philips Semiconductors

Product speciﬁcation

8-bit addressable latch

74HC/HCT259

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”.

Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input.

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

(1) HC : VM = 50%; VI = GND to VCC.

HCT: VM = 1.3 V; VI = GND to 3 V.

Número de pieza similar - 74HC259PW

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
NXP Semiconductors	74HC259PW	134Kb / 21P	8-bit addressable latch Rev. 04-25 February 2009
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Nexperia B.V. All right...	74HC259PW	316Kb / 18P	8-bit addressable latch Rev. 8 - 5 December 2022
NXP Semiconductors	74HC259PW-Q100	261Kb / 20P	8-bit addressable latch Rev. 1-30 July 2012
Nexperia B.V. All right...	74HC259PW-Q100	287Kb / 17P	8-bit addressable latch Rev. 2 - 2 September 2020

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