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74LVC11PWDH Datasheet(PDF) 2 Page - NXP Semiconductors |
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74LVC11PWDH Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74LVC11 Triple 3-input AND gate 2 1998 Apr 28 853-2060 19308 FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output capability: standard • I CC category: SSI DESCRIPTION The 74LVC11 is a high-performance, low power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC11 provides the 3-input AND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nA, nB, nC to nY CL = 50 pF; VCC = 3.3 V 3.7 ns CI Input capacitance 5.0 pF CPD Power dissipation capacitance per gate Notes 1 and 2 26 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO –40 °C to +85°C 74LVC11 D 74LVC11 D SOT108-1 14-Pin Plastic SSOP Type II –40 °C to +85°C 74LVC11 DB 74LVC11 DB SOT337-1 14-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVC11 PW 74LVC11PW DH SOT402-1 PIN CONFIGURATION SV00416 1 2 3 4 5 6 7 1A 1B 2A 2B 2C 2Y GND V CC 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9 8 LOGIC SYMBOL (IEEE/IEC) SV00439 5 1 2 12 4 6 8 9 10 11 13 & & & 3 |
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