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74LVC652 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC652 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 14 page Philips Semiconductors Product specification 74LVC652 Octal transceiver/register with dual enable (3-State) 1998 Jul 29 3 PIN CONFIGURATION SV00767 1 2 3 4 5 6 7 8 9 10 11 12 CP AB S AB OE AB A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 GND V CC CP BA S BA OE BA B 0 B 1 B 2 B 3 B 4 B 5 B 6 B 7 24 23 22 21 20 19 18 17 16 15 14 13 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 CPAB ‘A’ to ‘B’ clock input (LOW-to-HIGH, edge-triggered) 2 SAB Select ‘A’ to ‘B’ source input 3 OEAB Output enable B to A input (active LOW) 4, 5, 6, 7, 8, 9, 10, 11 A0 to A7 ‘A’ data inputs/outputs 12 GND Ground (0V) 20, 19, 18, 17, 16, 15, 14, 13 B0 to B7 ‘B’ data inputs/outputs 21 OEBA Output enable A to B input 22 SBA Select ‘B’ to ‘A’ source input 23 CPBA ‘B’ to ‘A’ clock input (LOW-to-HIGH, edge-triggered) 24 VCC Positive supply voltage FUNCTION TABLE INPUTS DATA I/O * FUNCTION OEAB OEBA CPAB CPBA SAB SBA A0 to A7 B0 to B7 FUNCTION L L H H H or L ↑ H or L ↑ X X X X input input isolation store A and B data X H H H ↑ ↑ H or L ↑ X L X X input input un * output store A, hold B, store A in both registers L L X L H or L ↑ ↑ ↑ X X X L un * output input input hold A, store B, store B in both registers L L L L X X X H or L X X L H output input real-time B data to A bus stored B data to A bus H H H H X H or L X X L H X X input output real-time A data to B bus stored A data to B bus H L H or L H or L H H output output stored A data to B bus and stored B data to A bus * The data output functions may be enabled or disabled by various signals at the OEAB and OEBA inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. un = unspecified H = HIGH voltage level L = LOW voltage level X = Don’t care ↑ = LOW–to–HIGH level transition |
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