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74LVT16500ADL Datasheet(PDF) 4 Page - NXP Semiconductors |
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74LVT16500ADL Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 14 page Philips Semiconductors Product specification 74LVT16500A 3.3V 18-bit universal bus transceiver (3-State) 1998 Feb 19 4 FUNCTION TABLE INPUTS Internal OUTPUTS OPERATING MODE OEAB LEAB CPAB An Registers Bn L H X X X Z Disabled L ↓ X h H Z Disabled Latch data L ↓ X I L Z Disabled, Latch data L L H or L X NC Z Disabled, Hold data L L ↓ h H Z Disabled Clock data L L ↓ I L Z Disabled, Clock data H H X H H H Transparent H H X L L L Transparent H ↓ X h H H Latch data & display H ↓ X I L L Latch data & display H L ↓ h H H Clock data & display H L ↓ I L L Clock data & display H L H or L X H H Hold data & display H L H or L X L L Hold data & display NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA. H = High voltage level h = High voltage level one set-up time prior to the Enable or Clock transition L = Low voltage level I = Low voltage level one set-up time prior to the Enable or Clock transition NC= No Change X = Don’t care Z = High Impedance ”off” state ↓ = High-to-Low Enable or Clock transition |
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