Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

MC145481 Datasheet(PDF) 9 Page - Motorola, Inc

No. de pieza MC145481
Descripción Electrónicos  3V PCM CODEC-FILTER
Download  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC145481 Datasheet(HTML) 9 Page - Motorola, Inc

Back Button MC145481 Datasheet HTML 5Page - Motorola, Inc MC145481 Datasheet HTML 6Page - Motorola, Inc MC145481 Datasheet HTML 7Page - Motorola, Inc MC145481 Datasheet HTML 8Page - Motorola, Inc MC145481 Datasheet HTML 9Page - Motorola, Inc MC145481 Datasheet HTML 10Page - Motorola, Inc MC145481 Datasheet HTML 11Page - Motorola, Inc MC145481 Datasheet HTML 12Page - Motorola, Inc MC145481 Datasheet HTML 13Page - Motorola, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 23 page
background image
MC145481
MOTOROLA
9
FSR pin controls whether the B1 channel or the B2 channel
is used for both transmit and receive PCM data word trans-
fers. When the FSR pin is low, the transmit and receive PCM
words are transferred in the B1 channel, and for FSR high
the B2 channel is selected. The start of the B2 channel is ten
IDL CLK cycles after the start of the B1 channel.
The IDL SYNC (FST, Pin 14) is the input for the IDL frame
synchronization signal. The signal at this pin is nominally
high for one cycle of the IDL Clock signal and is rising edge
aligned with the IDL Clock signal. (Refer to Figure 4 and the
IDL Timing specifications for more details.) This event identi-
fies the beginning of the IDL frame. The frequency of the IDL
Sync signal is 8 kHz. The rising edge of the IDL SYNC (FST)
should be aligned approximately with the rising edge of
MCLK. MCLK must be one of the clock frequencies specified
in the Digital Switching Characteristics table, and is typically
tied to IDL CLK (BCLKT).
The IDL CLK (BCLKT, Pin 12) is the input for the PCM
data clock. All IDL PCM transfers and data control sequenc-
ing are controlled by this clock following the IDL SYNC. This
pin accepts an IDL data clock frequency of 256 kHz to 4.096
MHz.
The IDL TX (DT, Pin 13) is the output for the transmit PCM
data word. Data bits are output for the B1 channel on se-
quential rising edges of the IDL CLK signal beginning after
the IDL SYNC pulse. If the B2 channel is selected, then the
PCM word transfer starts on the eleventh IDL CLK rising
edge after the IDL SYNC pulse. The IDL TX pin will remain
low impedance for the duration of the PCM word until the
LSB after the falling edge of IDL CLK. The IDL TX pin will re-
main in a high impedance state when not outputting PCM
data or when a valid IDL Sync signal is missing.
The IDL RX (DR, Pin 8) is the input for the receive PCM
data word. Data bits are input for the B1 channel on sequen-
tial falling edges of the IDL CLK signal beginning after the
IDL SYNC pulse. If the B2 channel is selected, then the PCM
word is latched in starting on the eleventh IDL CLK falling
edge after the IDL SYNC pulse.
General Circuit Interface (GCI)
The General Circuit Interface (GCI) is the second of two
standard synchronous 2B+D ISDN timing interface modes
with which this device is compatible. In the GCI mode, the
device can communicate in either of the two 64 kbps B–
channels. (Refer to Figure 2d for sample timing.) The GCI
mode is selected when the BCLKR pin is held low for two or
more FST (FSC) rising edges. The digital pins that control
the transmit and receive PCM word transfers are repro-
grammed to accommodate this mode. The pins affected are
FST, FSR, BCLKT, DT, and DR. The GCI Interface consists
of four pins: FSC (FST), DCL (BCLKT), Dout (DT), and Din
(DR). The GCI interface mode provides access to both the
transmit and receive PCM data words with common control
clocks of FSC (frame synchronization clock) and DCL (data
clock). In this mode, the FSR pin controls whether the B1
channel or the B2 channel is used for both transmit and re-
ceive PCM data word transfers. When the FSR pin is low, the
transmit and receive PCM words are transferred in the B1
channel, and for FSR high the B2 channel is selected. The
start of the B2 channel is 16 DCL cycles after the start of the
B1 channel.
The FSC (FST, Pin 14) is the input for the GCI frame syn-
chronization signal. The signal at this pin is nominally rising
edge aligned with the DCL clock signal. (Refer to Figure 6
and the GCI Timing specifications for more details.) This
event identifies the beginning of the GCI frame. The frequen-
cy of the FSC synchronization signal is 8 kHz. The rising
edge of the FSC (FST) should be aligned approximately with
the rising edge of MCLK. MCLK must be one of the clock fre-
quencies specified in the Digital Switching Characteristics
table, and is typically tied to DCL (BCLKT).
The DCL (BCLKT, Pin 12) is the input for the clock that
controls the PCM data transfers. The clock applied at the
DCL input is twice the actual PCM data rate. The GCI frame
begins with the logical AND of the FSC with the DCL. This
event initiates the PCM data word transfers for both transmit
and receive. This pin accepts a GCI data clock frequency of
512 kHz to 6.176 MHz for PCM data rates of 256 kHz to
3.088 MHz.
The GCI Dout (DT, Pin 13) is the output for the transmit
PCM data word. Data bits are output for the B1 channel on
alternate rising edges of the DCL clock signal, beginning with
the FSC pulse. If the B2 channel is selected, then the PCM
word transfer starts on the seventeenth DCL rising edge after
the FSC rising edge. The Dout pin will remain low impedance
for 15–1/2 DCL clock cycles. The Dout pin becomes high
impedance after the second falling edge of the DCL clock
during the LSB of the PCM word. The Dout pin will remain in
a high–impedance state when not outputting PCM data or
when a valid FSC signal is missing.
The Din (DR, Pin 8) is the input for the receive PCM data
word. Data bits are latched in for the B1 channel on alternate
rising edges of the DCL clock signal, beginning with the se-
cond DCL clock after the rising edge of the FSC pulse. If the
B2 channel is selected then the PCM word is latched in start-
ing on the eighteenth DCL rising edge after the FSC rising
edge.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
The MC145481 is manufactured using high–speed CMOS
VLSI technology to implement the complex analog signal
processing functions of a PCM Codec–Filter. The fully–differ-
ential analog circuit design techniques used for this device
result in superior performance for the switched capacitor fil-
ters, the analog–to–digital converter (ADC) and the digital–
to–analog converter (DAC). Special attention was given to
the design of this device to reduce the sensitivities of noise,
including power supply rejection and susceptibility to radio
frequency noise. This special attention to design includes a
fifth order low–pass filter, followed by a third order high–pass
filter whose output is converted to a digital signal with greater
than 75 dB of dynamic range, all operating on a single 3 V
power supply. This results in an LSB size for small audio sig-
nals of about 216
µV. The typical idle channel noise level of
this device is less than one LSB. In addition to the dynamic
range of the codec–filter function of this device, the input
gain–setting op amp has the capability of greater than 30 dB
of gain intended for an electret microphone interface.
This device was designed for ease of implementation, but
due to the large dynamic range and the noisy nature of the
environment for this device (digital switches, radio tele-


Número de pieza similar - MC145481

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Motorola, Inc
MC145480 MOTOROLA-MC145480 Datasheet
418Kb / 24P
   5V PCM CODEC-FILTER
MC145480DW MOTOROLA-MC145480DW Datasheet
418Kb / 24P
   5V PCM CODEC-FILTER
MC145480P MOTOROLA-MC145480P Datasheet
418Kb / 24P
   5V PCM CODEC-FILTER
MC145480VF MOTOROLA-MC145480VF Datasheet
418Kb / 24P
   5V PCM CODEC-FILTER
MC145482 MOTOROLA-MC145482 Datasheet
221Kb / 19P
   5V 13-BIT LINEAR PCM CODEC-FILTER
More results

Descripción similar - MC145481

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Motorola, Inc
MC145483 MOTOROLA-MC145483 Datasheet
220Kb / 19P
   3V 13-BIT LINEAR PCM CODEC-FILTER
logo
KODENSHI_AUK CORP.
KK145567 KODENSHI-KK145567 Datasheet
373Kb / 10P
   PCM CODEC - FILTER
logo
Motorola, Inc
MC145554 MOTOROLA-MC145554 Datasheet
342Kb / 20P
   PCM Codec-Filter
logo
LANSDALE Semiconductor ...
ML145554 LANSDALE-ML145554 Datasheet
1Mb / 18P
   PCM Codec-Filter
logo
Integral Corp.
IL145567 INTEGRAL-IL145567 Datasheet
355Kb / 10P
   PCM CODEC - FILTER
logo
LANSDALE Semiconductor ...
ML145554 LANSDALE-ML145554_08 Datasheet
284Kb / 18P
   PCM Codec-Filter
logo
Motorola, Inc
MC145484 MOTOROLA-MC145484 Datasheet
293Kb / 26P
   5V PCM CODEC-FILTER
MC145480 MOTOROLA-MC145480 Datasheet
418Kb / 24P
   5V PCM CODEC-FILTER
logo
National Semiconductor ...
TP3094 NSC-TP3094 Datasheet
186Kb / 19P
   Quad PCM Codec/Filter
logo
NXP Semiconductors
MC145484 NXP-MC145484 Datasheet
607Kb / 28P
   5V PCM Codec-Filter
REV 2 3/98
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com