AU2901 datasheet(4/10 Pages) PHILIPS | Quad voltage comparator

4 page

Philips Semiconductors

Product data

AU2901

Quad voltage comparator

2001 Aug 03

ELECTRICAL CHARACTERISTICS

V+ = 5 VDC; –40 °C ≤ Tamb ≤ 125 °C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

Limits

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNIT

VOS

Input offset voltage2

Tamb = 25 °C

±2.0

±3

VOS

In ut offset voltage

Over temp.

±2.5

±5

VCM

Input common-mode voltage range3

Tamb = 25 °C

V+ –1.5

VCM

In ut common-mode voltage range

Over temp.

V+ –2.0

VIDR

Differential input voltage1

Keep all VINs ≥ 0VDC (or V– if need)

V+

IIN(+) or IIN(–) with output in linear range

IBIAS

Input bias current4

Tamb = 25 °C

250

Over temp.

200

500

IIN(+) – IIN(–)

IOS

Input offset current

Tamb = 25 °C

±5

±50

Over temp.

±50

±200

IOL

Output sink current

VIN(–) ≥ 1 VDC; VIN(+) = 0; VO ≤ 1.5 VDC;

Tamb = 25 °C

6.0

VIN(+) ≥ 1 VDC; VIN(–) = 0

IOH

Output leakage current

VO = 5 VDC; Tamb = 25 °C

0.1

VO = 30 VDC; Over temp.

1.0

µA

RL = ∞ on comparators,

ICC

Supply current

Tamb = 25 °C

0.8

2.0

V+ = 30 V

1.0

2.5

Voltage gain

RL ≥ 15 kΩ; V+ = 15 VDC

100

V/mV

VIN(–) ≥ 1 VDC; VIN(+) = 0; ISINK ≤ 4 mA

VOL

Saturation voltage

Tamb = 25 °C

400

Over temp.

400

700

t S

Large signal response time

VIN = TTL logic swing; VREF = 1.4VDC;

300

tLSR

Large–signal response time

REF

VRL = 5VDC; RL = 5.1 kΩ; Tamb = 25 °C

300

Response time5

VRL = 5 VDC; RL = 5.1 kΩ; Tamb = 25 °C

1.3

µs

NOTES:

1. Positive excursions of input voltage may exceed the power supply level by 17 V. As long as the other voltage remains within the

common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than –0.3 VDC (or

0.3 VDC below the magnitude of the negative power supply, if used).

2. At output switch point, VO ≈ 1.4 VDC, RS = 0 Ω with V+ from 5 VDC to 30 VDC; and over the full input common-mode range (0 VDC to

V+ – 1.5 VDC).

3. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of

the common-mode voltage range is V+ – 1.5 V, but either or both inputs can go to 30 VDC without damage.

4. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of

the output so no loading change exists on the reference or input lines.

5. The response time specified is for a 100 mV input step with a 5 mV overdrive. For larger overdrive signals, 300 ns can be obtained (see

Typical Performance Characteristics section).

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