TL16C752B-EP

3.3-V DUAL UART WITH 64-BYTE FIFO

SGLS153 – FEBRUARY 2003

1

POST OFFICE BOX 655303

– One Assembly/Test Site, One Fabrication

Site

–40

°C to 110°C

Sources (DMS) Support

Additional Enhancements

Crystal (24-MHz Input Clock)

Oscillator or Clock Source (48-MHz Input

Clock)

Receive FIFO Trigger Levels for DMA and

Interrupt Generation

for Software/Hardware Flow Control

– Programmable Xon/Xoff Characters

– Programmable Auto-RTS and Auto-CTS

Character

Received and Transmitted Data

Four Function

Pulse Width

Characteristics

– 5-, 6-, 7-, or 8-Bit Characters

– Even, Odd, or No Parity Bit Generation

and Detection

– 1, 1.5, or 2 Stop Bit Generation

Both Normal and Sleep Mode

DTR, RI, and CD)

description

The TL16C752B-EP is a dual-universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs,

automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B-EP offers enhanced

features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop

transmission during hardware and software flow control. With the FIFO RDY register, the software gets the

status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error

indications, operational status, and modem interface control. System interrupts may be tailored to meet user

requirements. An internal loopback capability allows onboard diagnostics.

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on

the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO

and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own

desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity

and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors.

The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control

operations, and has software flow control and hardware flow control capabilities.

† Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.

This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this

component beyond specified performance and environmental limits.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright

 2003, Texas Instruments Incorporated