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TPA5052RSARG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPA5052RSARG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 10 page www.ti.com PIN DESCRIPTIONS DEL1 LRCLK DEL3 GND DEL0 DEL2 DATA 11 9 10 12 3 1 2 4 DEL4 TPA5052 SLOS500A – JUNE 2006 – REVISED AUGUST 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. RSA (QFN) PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. DEL0 10 I Delay select pin – LSB. 5V tolerant input. DEL1 11 I Delay select pin. 5V tolerant input. DEL2 12 I Delay select pin. 5V tolerant input. DEL3 3 I Delay select pin. 5V tolerant input. DEL4 4 I Delay select pin - MSB. 5V tolerant input. BCLK 16 I Audio data bit clock input for serial input. 5V tolerant input. DATA 2 I Audio serial data input for serial input. 5V tolerant input. DATA_OUT 15 O Delayed audio serial data output. GND 5–9 P Ground – All ground terminals must be tied to GND for proper operation LRCLK 1 I Left and Right serial audio sampling rate clock (fs). 5V tolerant input. VDD 13, 14 P Power supply interface. Both pins must be tied to power supply. Connect to ground. Must be soldered down in all applications to properly secure device on the Thermal Pad - PCB. 2 Submit Documentation Feedback |
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