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TPA5052RSATG4 Datasheet(PDF) 5 Page - Texas Instruments |
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TPA5052RSATG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 10 page www.ti.com APPLICATION INFORMATION AUDIO SERIAL INTERFACE I2S TIMING 1/fS (=32fS,48fS, or64fS) L-Channel R-Channel LRCK BCK DATA 1 2 3 1 2 MSB N–2 N N–1 LSB 1 2 3 MSB N–2 N N–1 LSB GENERAL DELAY OPERATION TPA5052 SLOS500A – JUNE 2006 – REVISED AUGUST 2006 The audio serial interface for the TPA5052 consists of a 3-wire synchronous serial port. It includes LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the TPA5052 on the rising edge of BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64 times the sampling frequency for I2S formats. A system clock is not necessary for the operation of the TPA5052. The I2S data format diagram is shown in Figure 2. Figure 2. I2S Data Format; L-Channel = LOW, R-Channel = HIGH The delay of the TPA5052 is set using the 5 delay pins (DEL4, DEL3, DEL2, DEL1, DEL0). The minimum delay is 255 samples, and occurs when all five pins are at logic 0. The maximum delay is 8191 samples, and occurs when all five pins are at logic 1. The delay can be increased by changing the values on each pin from a 0 to a 1. See Table 1. Delay pin DEL4 is the MSB, and DEL0 is the LSB. The delay is calculated with the following forumula: Audio Delay (in samples) = 4096 x (DEL4) + 2048 x (DEL3) + 1024 x (DEL2) + 512 x (DEL1) + 256 x (DEL0) + 255 Audio Delay (ms) = Audio Delay (in samples) x (1/fs) Both channels have the same amount of delay. They cannot be controlled individually. Table 1. Delay Settings DEL4 DEL3 DEL2 DEL1 DEL0 Delay in Samples 0 0 0 0 0 255 0 0 0 0 1 511 0 0 0 1 0 767 0 0 0 1 1 1023 ↓ ↓ ↓ ↓ ↓ ↓ 1 1 1 1 1 8191 5 Submit Documentation Feedback |
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