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ST7260 Datasheet(PDF) 7 Page - STMicroelectronics |
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ST7260 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 117 page ST7260 7/117 PIN DESCRIPTION (Cont’d) RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is trig- gered or the VDD is low. It can be used to reset ex- ternal peripherals. OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. VDD/VSS (see Note 2): Main Power Supply and Ground voltages. VDDA/VSSA (see Note 2): Power Supply and Ground voltages for analog peripherals. Alternate Functions: Several pins of the I/O ports assume software programmable alternate func- tions as shown in the pin description. Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to V DD and V SS) will significantly improve product electro- magnetic susceptibility performance. Note 2: To enhance the reliability of operation, it is recommended that VDDA and VDD be connected to- gether on the application board. This also applies to VSSA and VSS. Note 3: The USBOE alternate function is mapped on Port C2 in QFN40 devices. In SO24 devices it is mapped on Port B1. Note 4: The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24 devices it is not available. Legend / Abbreviations for Table 2, Table 3: Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3 VDD / 0.7 VDD with input trigger Output level: 10 mA = 10 mA high sink (Fn N-buffer only) 25 mA = 25 mA very high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt – Output: OD = open drain, PP = push-pull, T = True open drain The RESET configuration of each pin is shown in bold. This configuration is kept as long as the de- vice is under reset state. |
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