ADCMP608 datasheet(6/16 Pages) AD | Rail-to-Rail, Fast, Low Power, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators

6 page

ADCMP608/ADCMP609

Preliminary Technical Data

Rev. PrA | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADCMP608

TOP VIEW

(Not to Scale)

Q 1

VCC

VEE 2

SDN

VP 3

ADCMP609

TOP VIEW

(Not to Scale)

VCC 1

VP 2

VN 3

VEE

SDN 4

LE/HYS

Figure 2. ADCMP608 Pin Configuration

Figure 3. ADCMP609 Pin Configuration

Table 4. ADCMP608 Pin Function Descriptions

Pin No.

Mnemonic

Description

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the

analog voltage at the inverting input, VN.

VEE

Negative Supply Voltage.

Noninverting Analog Input.

Inverting Analog Input.

SDN

Shutdown. Drive this pin low to shutdown the device.

VCC

VCC Supply.

Table 5. ADCMP609 Pin Function Descriptions

Pin No.

Mnemonic

Description

VCCI/VCCO

Vcc Supply.

Noninverting Analog Input.

Inverting Analog Input.

SDN

Shutdown. Drive this pin low to shutdown the device.

LE/HYS

Latch/Hysteresis Control. Bias with resistor or current source for hysteresis; drive TTL low to latch.

VEE

Negative Supply Voltage.

Noninverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the

analog voltage at the inverting input, VN, provided the comparator is in compare mode.

Inverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog

voltage at the inverting input, VN, provided the comparator is in compare mode.

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