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REV. 0 –6– ADF4251 ADF4251 2 DOUBLER OUTPUT MUX 4-BIT R COUNTER PHASE FREQUENCY DETECTOR LOCK DETECT CHARGE PUMP REFERENCE REFIN VDD1 VDD2 VDD3 DVDD VP1 VP2RSET 24-BIT DATA REGISTER CLK DATA LE RFINA RFINB CPRF CPIF 2 DOUBLER 15-BIT R COUNTER CHARGE PUMP PHASE FREQUENCY DETECTOR MUXOUT AGND1 AGND2 DGND CPGND1 CPGND2 IFINB IFINA FRACTIONAL N RF DIVIDER INTEGER N IF DIVIDER CE FROM REFIN Figure 2. Detailed Functional Block Diagram |
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