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AD5372BCPZ Datasheet(PDF) 5 Page - Analog Devices |
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AD5372BCPZ Datasheet(HTML) 5 Page - Analog Devices |
5 / 25 page Preliminary Technical Data AD5372/AD5373 Rev. P rF | Page 5 of 25 Parameter AD53721 B Version AD53731 B Version Unit Test Conditions/Comments2 POWER REQUIREMENTS DVCC 2.3/5.5 2.3/5.5 V min/max VDD 8/16.5 8/16.5 V min/max VSS −4.5/−16.5 −4.5/−16.5 V min/max Power Supply Sensitivity2 ∆ Full Scale/∆ VDD −75 −75 dB typ ∆ Full Scale/∆ VSS −75 −75 dB typ ∆ Full Scale/∆ VCC −90 −90 dB typ DICC 2 2 mA max VCC = 5.5 V, VIH = VCC, VIL = GND. IDD 14 14 mA max Outputs unloaded. ISS 14 14 mA max Outputs unloaded. Power Dissipation Power Dissipation Unloaded (P) 350 350 mW Junction Temperature3 130 130 °C max TJ = TA + PTOTAL × θJ. 1 Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C. 2 Guaranteed by design and characterization, not production tested. 3 Where θJ represents the package thermal impedance. AC CHARACTERISTICS DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 kΩ; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted. Table 3. AC Characteristics Parameter AD5372/ AD5373 Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Output Voltage Settling Time 20 µs typ Full-scale change 30 µs max DAC latch contents alternately loaded with all 0s and all 1s. Slew Rate 1 V/µs typ Digital-to-Analog Glitch Energy 20 nV-s typ Glitch Impulse Peak Amplitude 10 mV max Channel-to-Channel Isolation 100 dB typ VREF(+) = 2 V p-p, 1 kHz. DAC-to-DAC Crosstalk 40 nV-s typ Between DACs in the same group. 10 nV-s typ Between DACs from different groups. Digital Crosstalk 0.1 nV-s typ Digital Feedthrough 1 nV-s typ Effect of input bus activity on DAC output under test. Output Noise Spectral Density @ 10 kHz 250 nV/(Hz)1/2 typ VREF = 0 V. 1Guaranteed by design and characterization. Not production tested |
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