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AD7367BRUZ-REEL7 Datasheet(PDF) 9 Page - Analog Devices |
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AD7367BRUZ-REEL7 Datasheet(HTML) 9 Page - Analog Devices |
9 / 40 page AD7329 Rev. 0 | Page 9 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 DIN DGND AGND ADCIN+ VSS REFIN/REFOUT CS DGND DOUT VDRIVE ADCIN– VDD VCC MUXOUT+ VIN0 VIN5 VIN4 VIN1 MUXOUT– VIN2 VIN7 VIN6 VIN3 SCLK AD7329 TOP VIEW (Not to Scale) Figure 3. TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Descriptions 24 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7329. This clock is also used as the clock source for the conversion process. 22 DOUT Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the Serial Interface section). 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7329 and frames the serial data transfer. 2 DIN Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the Registers section). 21 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin can be different than that at VCC but should not exceed VCC by more than 0.3 V. 3, 23 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7329. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 4 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7329. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 5 REFIN/REFOUT Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7329. Alternatively, the internal reference can be disabled and an external reference applied to this input. On power up, this is the default condition. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor should be placed on the reference pin (see the Reference section). 20 VCC Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7329. This supply should be decoupled to AGND. 19 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. 6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. 7 ADCIN+ Positive ADC Input. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still a high voltage signal (±10 V, ±5 V, ±2.5 V, or 0 V to +10 V). 8 MUXOUT+ Positive Multiplexer Output. The output of the multiplexer appears at this pin. The voltage at this pin is still a high voltage signal equivalent to the voltage applied to the VIN+ input channel, as selected in the control register or sequence register. If no external filtering or buffering is required, this pin should be tied to the ADCIN+ pin. |
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